726d32bf79
SoC identification code, kernel uncompress and low level debugging routines update. On SAMA5D4, DBGU is at another address AT91_BASE_DBGU2 so another round of detection is needed. We also had to differentiate with SAMA5D3 SoC family and rename some variables. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
64 lines
1.8 KiB
C
64 lines
1.8 KiB
C
/*
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* Chip-specific setup code for the SAMA5D4 family
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*
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* Copyright (C) 2013 Atmel Corporation,
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* Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk/at91_pmc.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/sama5d4.h>
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#include <mach/cpu.h>
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#include <mach/hardware.h>
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#include "soc.h"
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#include "generic.h"
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#include "sam9_smc.h"
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/* --------------------------------------------------------------------
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* Processor initialization
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* -------------------------------------------------------------------- */
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static struct map_desc at91_io_desc[] __initdata = {
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{
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.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
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.pfn = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
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.length = SZ_512,
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.type = MT_DEVICE,
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},
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{
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.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
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.pfn = __phys_to_pfn(SAMA5D4_BASE_PMC),
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.length = SZ_512,
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.type = MT_DEVICE,
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},
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{ /* On sama5d4, we use USART3 as serial console */
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.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
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.pfn = __phys_to_pfn(SAMA5D4_BASE_USART3),
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.length = SZ_256,
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.type = MT_DEVICE,
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},
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{ /* A bunch of peripheral with fine grained IO space */
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.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
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.pfn = __phys_to_pfn(SAMA5D4_BASE_SYS2),
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.length = SZ_2K,
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.type = MT_DEVICE,
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},
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};
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static void __init sama5d4_map_io(void)
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{
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iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
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at91_init_sram(0, SAMA5D4_NS_SRAM_BASE, SAMA5D4_NS_SRAM_SIZE);
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}
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AT91_SOC_START(sama5d4)
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.map_io = sama5d4_map_io,
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AT91_SOC_END
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