a39a493932
Add a reset-controller driver for the socfpga platform.
The reset-controller has four banks with up to 32 entries all encapsulated in
one module block.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
Notes:
Changes since v2:
- remove superfluous ret in probe function
- add Acked-by
Changes since v1:
- use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
- print pdev->dev.of_node->full_name on error
- use proper IS_ERR/PTR_ERR
146 lines
3.7 KiB
C
146 lines
3.7 KiB
C
/*
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* Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
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*
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* based on
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* Allwinner SoCs Reset Controller driver
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*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define NR_BANKS 4
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#define OFFSET_MODRST 0x10
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struct socfpga_reset_data {
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spinlock_t lock;
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void __iomem *membase;
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struct reset_controller_dev rcdev;
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};
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static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct socfpga_reset_data *data = container_of(rcdev,
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struct socfpga_reset_data,
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rcdev);
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int bank = id / BITS_PER_LONG;
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int offset = id % BITS_PER_LONG;
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&data->lock, flags);
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reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
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writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
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(bank * NR_BANKS));
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct socfpga_reset_data *data = container_of(rcdev,
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struct socfpga_reset_data,
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rcdev);
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int bank = id / BITS_PER_LONG;
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int offset = id % BITS_PER_LONG;
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&data->lock, flags);
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reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
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writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
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(bank * NR_BANKS));
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static struct reset_control_ops socfpga_reset_ops = {
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.assert = socfpga_reset_assert,
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.deassert = socfpga_reset_deassert,
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};
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static int socfpga_reset_probe(struct platform_device *pdev)
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{
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struct socfpga_reset_data *data;
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struct resource *res;
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/*
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* The binding was mainlined without the required property.
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* Do not continue, when we encounter an old DT.
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*/
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if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
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dev_err(&pdev->dev, "%s missing #reset-cells property\n",
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pdev->dev.of_node->full_name);
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return -EINVAL;
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}
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(data->membase))
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return PTR_ERR(data->membase);
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spin_lock_init(&data->lock);
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
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data->rcdev.ops = &socfpga_reset_ops;
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data->rcdev.of_node = pdev->dev.of_node;
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reset_controller_register(&data->rcdev);
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return 0;
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}
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static int socfpga_reset_remove(struct platform_device *pdev)
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{
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struct socfpga_reset_data *data = platform_get_drvdata(pdev);
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reset_controller_unregister(&data->rcdev);
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return 0;
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}
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static const struct of_device_id socfpga_reset_dt_ids[] = {
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{ .compatible = "altr,rst-mgr", },
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{ /* sentinel */ },
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};
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static struct platform_driver socfpga_reset_driver = {
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.probe = socfpga_reset_probe,
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.remove = socfpga_reset_remove,
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.driver = {
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.name = "socfpga-reset",
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.owner = THIS_MODULE,
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.of_match_table = socfpga_reset_dt_ids,
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},
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};
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module_platform_driver(socfpga_reset_driver);
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MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de");
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MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
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MODULE_LICENSE("GPL");
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