a87010ef32
SiRF internal interrupts are using level trigger. we need to tell the irq core this information. otherwise, we might get some problems as below 1. disable_irq(n) here irq core will mark the disabled flag but still keep the irq enabled due to involved lazy-disable 2. doing someting after disable_irq(n) in step 2, if one interrupt n comes, irq core will mark it as pending and mask the HW interrupt really. we name the coming interrupt as "X". 3. enable_irq(n) this will unmask the interrupt, so the level-trigger HW interrupt will come again, irq_handler will enter as "E1". after that, irq core will also check whether irq n is pending, if yes, and pending interrupt is not level-trigger, irq core will execute the pending irq_handler. so if we don't set the IRQ_LEVEL flag here, irq core will execute pending X again as "E2", but actually the pending interrupt has been handled by "E1". that makes a level-trigger HW interrupt is executed twice. here we fix the issue to avoid redundant interrupt overload. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Olof Johansson <olof@lixom.net>
129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
/*
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* interrupt controller support for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irqdomain.h>
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#include <linux/syscore_ops.h>
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#include <asm/mach/irq.h>
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#include <asm/exception.h>
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#include "irqchip.h"
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#define SIRFSOC_INT_RISC_MASK0 0x0018
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#define SIRFSOC_INT_RISC_MASK1 0x001C
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#define SIRFSOC_INT_RISC_LEVEL0 0x0020
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#define SIRFSOC_INT_RISC_LEVEL1 0x0024
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#define SIRFSOC_INIT_IRQ_ID 0x0038
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#define SIRFSOC_NUM_IRQS 64
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static struct irq_domain *sirfsoc_irqdomain;
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static __init void
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sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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int ret;
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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unsigned int set = IRQ_LEVEL;
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ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
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handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE);
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gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
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gc->reg_base = base;
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
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}
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static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
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{
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void __iomem *base = sirfsoc_irqdomain->host_data;
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u32 irqstat, irqnr;
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irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
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irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff);
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handle_IRQ(irqnr, regs);
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}
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static int __init sirfsoc_irq_init(struct device_node *np, struct device_node *parent)
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{
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void __iomem *base = of_iomap(np, 0);
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if (!base)
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panic("unable to map intc cpu registers\n");
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sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
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&irq_generic_chip_ops, base);
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sirfsoc_alloc_gc(base, 0, 32);
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sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);
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writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
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writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
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writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
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writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
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set_handle_irq(sirfsoc_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
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struct sirfsoc_irq_status {
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u32 mask0;
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u32 mask1;
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u32 level0;
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u32 level1;
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};
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static struct sirfsoc_irq_status sirfsoc_irq_st;
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static int sirfsoc_irq_suspend(void)
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{
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void __iomem *base = sirfsoc_irqdomain->host_data;
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sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
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sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
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sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
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sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
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return 0;
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}
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static void sirfsoc_irq_resume(void)
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{
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void __iomem *base = sirfsoc_irqdomain->host_data;
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writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
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writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
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writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
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writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
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}
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static struct syscore_ops sirfsoc_irq_syscore_ops = {
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.suspend = sirfsoc_irq_suspend,
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.resume = sirfsoc_irq_resume,
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};
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static int __init sirfsoc_irq_pm_init(void)
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{
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if (!sirfsoc_irqdomain)
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return 0;
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register_syscore_ops(&sirfsoc_irq_syscore_ops);
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return 0;
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}
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device_initcall(sirfsoc_irq_pm_init);
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