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	c149dcb5c6
	
	
	
		
			
			For Haswell and Broadwell, if the display power well has been disabled, the display audio controller divider values EM4 M VALUE and EM5 N VALUE will have been lost. The CDCLK frequency is required for reprogramming them to generate 24MHz HD-A link BCLK. So provide a private interface for the audio driver to query CDCLK. This is a stopgap solution until a more generic interface between audio and display drivers has been implemented. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Mengdong Lin <mengdong.lin@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
		
			
				
	
	
		
			37 lines
		
	
	
	
		
			1.6 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			37 lines
		
	
	
	
		
			1.6 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /**************************************************************************
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|  *
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|  * Copyright 2013 Intel Inc.
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|  * All Rights Reserved.
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|  *
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|  * Permission is hereby granted, free of charge, to any person obtaining a
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|  * copy of this software and associated documentation files (the
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|  * "Software"), to deal in the Software without restriction, including
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|  * distribute, sub license, and/or sell copies of the Software, and to
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|  * permit persons to whom the Software is furnished to do so, subject to
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|  * the following conditions:
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|  * The above copyright notice and this permission notice (including the
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|  * next paragraph) shall be included in all copies or substantial portions
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|  * of the Software.
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|  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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|  **************************************************************************/
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| 
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| #ifndef _I915_POWERWELL_H_
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| #define _I915_POWERWELL_H_
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| 
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| /* For use by hda_i915 driver */
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| extern int i915_request_power_well(void);
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| extern int i915_release_power_well(void);
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| extern int i915_get_cdclk_freq(void);
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| 
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| #endif				/* _I915_POWERWELL_H_ */
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