964d219b6a
Add arch/avr32/mach-*/include to include search path and copy all the files from include/asm/arch there. The old files will be removed once ARM does the same change and all common drivers are converted. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
113 lines
2.4 KiB
C
113 lines
2.4 KiB
C
/*
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* Static Memory Controller for AT32 chips
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* Inspired by the OMAP2 General-Purpose Memory Controller interface
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_AT32AP_SMC_H
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#define __ARCH_AT32AP_SMC_H
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/*
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* All timing parameters are in nanoseconds.
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*/
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struct smc_timing {
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/* Delay from address valid to assertion of given strobe */
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int ncs_read_setup;
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int nrd_setup;
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int ncs_write_setup;
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int nwe_setup;
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/* Pulse length of given strobe */
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int ncs_read_pulse;
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int nrd_pulse;
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int ncs_write_pulse;
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int nwe_pulse;
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/* Total cycle length of given operation */
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int read_cycle;
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int write_cycle;
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/* Minimal recovery times, will extend cycle if needed */
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int ncs_read_recover;
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int nrd_recover;
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int ncs_write_recover;
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int nwe_recover;
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};
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/*
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* All timing parameters are in clock cycles.
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*/
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struct smc_config {
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/* Delay from address valid to assertion of given strobe */
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u8 ncs_read_setup;
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u8 nrd_setup;
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u8 ncs_write_setup;
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u8 nwe_setup;
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/* Pulse length of given strobe */
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u8 ncs_read_pulse;
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u8 nrd_pulse;
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u8 ncs_write_pulse;
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u8 nwe_pulse;
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/* Total cycle length of given operation */
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u8 read_cycle;
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u8 write_cycle;
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/* Bus width in bytes */
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u8 bus_width;
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/*
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* 0: Data is sampled on rising edge of NCS
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* 1: Data is sampled on rising edge of NRD
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*/
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unsigned int nrd_controlled:1;
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/*
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* 0: Data is driven on falling edge of NCS
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* 1: Data is driven on falling edge of NWR
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*/
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unsigned int nwe_controlled:1;
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/*
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* 0: NWAIT is disabled
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* 1: Reserved
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* 2: NWAIT is frozen mode
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* 3: NWAIT in ready mode
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*/
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unsigned int nwait_mode:2;
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/*
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* 0: Byte select access type
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* 1: Byte write access type
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*/
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unsigned int byte_write:1;
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/*
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* Number of clock cycles before data is released after
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* the rising edge of the read controlling signal
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*
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* Total cycles from SMC is tdf_cycles + 1
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*/
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unsigned int tdf_cycles:4;
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/*
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* 0: TDF optimization disabled
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* 1: TDF optimization enabled
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*/
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unsigned int tdf_mode:1;
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};
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extern void smc_set_timing(struct smc_config *config,
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const struct smc_timing *timing);
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extern int smc_set_configuration(int cs, const struct smc_config *config);
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extern struct smc_config *smc_get_configuration(int cs);
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#endif /* __ARCH_AT32AP_SMC_H */
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