For additional coverage, BorisO and friends unknowlingly did swap AMD microcode with Intel microcode blobs in order to see what happens. What did happen on 32-bit was [ 5.722656] BUG: unable to handle kernel paging request at be3a6008 [ 5.722693] IP: [<c106d6b4>] load_microcode_amd+0x24/0x3f0 [ 5.722716] *pdpt = 0000000000000000 *pde = 0000000000000000 because there was a valid initrd there but without valid microcode in it and the container check happened *after* the relocated ramdisk handling on 32-bit, which was clearly wrong. While at it, take care of the ramdisk relocation on both 32- and 64-bit as it is done on both. Also, comment what we're doing because this code is a bit tricky. Reported-and-tested-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: http://lkml.kernel.org/r/1391460104-7261-1-git-send-email-bp@alien8.de Signed-off-by: H. Peter Anvin <hpa@zytor.com>
		
			
				
	
	
		
			395 lines
		
	
	
	
		
			9 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			395 lines
		
	
	
	
		
			9 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright (C) 2013 Advanced Micro Devices, Inc.
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 *
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 * Author: Jacob Shin <jacob.shin@amd.com>
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 * Fixes: Borislav Petkov <bp@suse.de>
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License version 2 as
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 * published by the Free Software Foundation.
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 */
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#include <linux/earlycpio.h>
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#include <linux/initrd.h>
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#include <asm/cpu.h>
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#include <asm/setup.h>
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#include <asm/microcode_amd.h>
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/*
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 * This points to the current valid container of microcode patches which we will
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 * save from the initrd before jettisoning its contents.
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 */
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static u8 *container;
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static size_t container_size;
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static u32 ucode_new_rev;
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u8 amd_ucode_patch[PATCH_MAX_SIZE];
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static u16 this_equiv_id;
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struct cpio_data ucode_cpio;
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/*
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 * Microcode patch container file is prepended to the initrd in cpio format.
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 * See Documentation/x86/early-microcode.txt
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 */
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static __initdata char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin";
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static struct cpio_data __init find_ucode_in_initrd(void)
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{
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	long offset = 0;
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	char *path;
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	void *start;
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	size_t size;
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#ifdef CONFIG_X86_32
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	struct boot_params *p;
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	/*
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	 * On 32-bit, early load occurs before paging is turned on so we need
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	 * to use physical addresses.
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	 */
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	p       = (struct boot_params *)__pa_nodebug(&boot_params);
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	path    = (char *)__pa_nodebug(ucode_path);
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	start   = (void *)p->hdr.ramdisk_image;
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	size    = p->hdr.ramdisk_size;
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#else
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	path    = ucode_path;
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	start   = (void *)(boot_params.hdr.ramdisk_image + PAGE_OFFSET);
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	size    = boot_params.hdr.ramdisk_size;
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#endif
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	return find_cpio_data(path, start, size, &offset);
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}
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static size_t compute_container_size(u8 *data, u32 total_size)
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{
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	size_t size = 0;
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	u32 *header = (u32 *)data;
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	if (header[0] != UCODE_MAGIC ||
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	    header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
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	    header[2] == 0)                            /* size */
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		return size;
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	size = header[2] + CONTAINER_HDR_SZ;
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	total_size -= size;
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	data += size;
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	while (total_size) {
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		u16 patch_size;
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		header = (u32 *)data;
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		if (header[0] != UCODE_UCODE_TYPE)
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			break;
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		/*
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		 * Sanity-check patch size.
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		 */
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		patch_size = header[1];
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		if (patch_size > PATCH_MAX_SIZE)
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			break;
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		size	   += patch_size + SECTION_HDR_SIZE;
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		data	   += patch_size + SECTION_HDR_SIZE;
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		total_size -= patch_size + SECTION_HDR_SIZE;
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	}
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	return size;
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}
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/*
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 * Early load occurs before we can vmalloc(). So we look for the microcode
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 * patch container file in initrd, traverse equivalent cpu table, look for a
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 * matching microcode patch, and update, all in initrd memory in place.
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 * When vmalloc() is available for use later -- on 64-bit during first AP load,
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 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
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 * load_microcode_amd() to save equivalent cpu table and microcode patches in
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 * kernel heap memory.
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 */
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static void apply_ucode_in_initrd(void *ucode, size_t size)
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{
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	struct equiv_cpu_entry *eq;
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	size_t *cont_sz;
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	u32 *header;
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	u8  *data, **cont;
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	u16 eq_id = 0;
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	int offset, left;
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	u32 rev, eax, ebx, ecx, edx;
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	u32 *new_rev;
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#ifdef CONFIG_X86_32
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	new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
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	cont_sz = (size_t *)__pa_nodebug(&container_size);
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	cont	= (u8 **)__pa_nodebug(&container);
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#else
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	new_rev = &ucode_new_rev;
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	cont_sz = &container_size;
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	cont	= &container;
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#endif
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	data   = ucode;
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	left   = size;
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	header = (u32 *)data;
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	/* find equiv cpu table */
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	if (header[0] != UCODE_MAGIC ||
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	    header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
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	    header[2] == 0)                            /* size */
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		return;
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	eax = 0x00000001;
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	ecx = 0;
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	native_cpuid(&eax, &ebx, &ecx, &edx);
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	while (left > 0) {
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		eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ);
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		*cont = data;
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		/* Advance past the container header */
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		offset = header[2] + CONTAINER_HDR_SZ;
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		data  += offset;
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		left  -= offset;
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		eq_id = find_equiv_id(eq, eax);
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		if (eq_id) {
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			this_equiv_id = eq_id;
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			*cont_sz = compute_container_size(*cont, left + offset);
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			/*
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			 * truncate how much we need to iterate over in the
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			 * ucode update loop below
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			 */
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			left = *cont_sz - offset;
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			break;
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		}
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		/*
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		 * support multiple container files appended together. if this
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		 * one does not have a matching equivalent cpu entry, we fast
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		 * forward to the next container file.
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		 */
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		while (left > 0) {
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			header = (u32 *)data;
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			if (header[0] == UCODE_MAGIC &&
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			    header[1] == UCODE_EQUIV_CPU_TABLE_TYPE)
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				break;
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			offset = header[1] + SECTION_HDR_SIZE;
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			data  += offset;
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			left  -= offset;
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		}
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		/* mark where the next microcode container file starts */
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		offset    = data - (u8 *)ucode;
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		ucode     = data;
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	}
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	if (!eq_id) {
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		*cont = NULL;
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		*cont_sz = 0;
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		return;
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	}
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	/* find ucode and update if needed */
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	native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);
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	while (left > 0) {
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		struct microcode_amd *mc;
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		header = (u32 *)data;
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		if (header[0] != UCODE_UCODE_TYPE || /* type */
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		    header[1] == 0)                  /* size */
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			break;
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		mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE);
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		if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id) {
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			if (!__apply_microcode_amd(mc)) {
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				rev = mc->hdr.patch_id;
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				*new_rev = rev;
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				/* save ucode patch */
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				memcpy(amd_ucode_patch, mc,
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				       min_t(u32, header[1], PATCH_MAX_SIZE));
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			}
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		}
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		offset  = header[1] + SECTION_HDR_SIZE;
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		data   += offset;
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		left   -= offset;
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	}
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}
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void __init load_ucode_amd_bsp(void)
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{
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	struct cpio_data cp;
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	void **data;
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	size_t *size;
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#ifdef CONFIG_X86_32
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	data =  (void **)__pa_nodebug(&ucode_cpio.data);
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	size = (size_t *)__pa_nodebug(&ucode_cpio.size);
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#else
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	data = &ucode_cpio.data;
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	size = &ucode_cpio.size;
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#endif
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	cp = find_ucode_in_initrd();
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	if (!cp.data)
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		return;
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	*data = cp.data;
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	*size = cp.size;
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	apply_ucode_in_initrd(cp.data, cp.size);
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}
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#ifdef CONFIG_X86_32
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/*
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 * On 32-bit, since AP's early load occurs before paging is turned on, we
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 * cannot traverse cpu_equiv_table and pcache in kernel heap memory. So during
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 * cold boot, AP will apply_ucode_in_initrd() just like the BSP. During
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 * save_microcode_in_initrd_amd() BSP's patch is copied to amd_ucode_patch,
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 * which is used upon resume from suspend.
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 */
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void load_ucode_amd_ap(void)
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{
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	struct microcode_amd *mc;
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	size_t *usize;
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	void **ucode;
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	mc = (struct microcode_amd *)__pa(amd_ucode_patch);
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	if (mc->hdr.patch_id && mc->hdr.processor_rev_id) {
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		__apply_microcode_amd(mc);
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		return;
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	}
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	ucode = (void *)__pa_nodebug(&container);
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	usize = (size_t *)__pa_nodebug(&container_size);
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	if (!*ucode || !*usize)
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		return;
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	apply_ucode_in_initrd(*ucode, *usize);
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}
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static void __init collect_cpu_sig_on_bsp(void *arg)
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{
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	unsigned int cpu = smp_processor_id();
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	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
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	uci->cpu_sig.sig = cpuid_eax(0x00000001);
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}
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static void __init get_bsp_sig(void)
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{
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	unsigned int bsp = boot_cpu_data.cpu_index;
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	struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
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	if (!uci->cpu_sig.sig)
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		smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
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}
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#else
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void load_ucode_amd_ap(void)
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{
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	unsigned int cpu = smp_processor_id();
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	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
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	struct equiv_cpu_entry *eq;
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	struct microcode_amd *mc;
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	u32 rev, eax;
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	u16 eq_id;
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	/* Exit if called on the BSP. */
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	if (!cpu)
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		return;
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	if (!container)
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		return;
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	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);
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	uci->cpu_sig.rev = rev;
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	uci->cpu_sig.sig = eax;
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	eax = cpuid_eax(0x00000001);
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	eq  = (struct equiv_cpu_entry *)(container + CONTAINER_HDR_SZ);
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	eq_id = find_equiv_id(eq, eax);
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	if (!eq_id)
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		return;
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	if (eq_id == this_equiv_id) {
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		mc = (struct microcode_amd *)amd_ucode_patch;
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		if (mc && rev < mc->hdr.patch_id) {
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			if (!__apply_microcode_amd(mc))
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				ucode_new_rev = mc->hdr.patch_id;
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		}
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	} else {
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		if (!ucode_cpio.data)
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			return;
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		/*
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		 * AP has a different equivalence ID than BSP, looks like
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		 * mixed-steppings silicon so go through the ucode blob anew.
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		 */
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		apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size);
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	}
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}
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#endif
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int __init save_microcode_in_initrd_amd(void)
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{
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	unsigned long cont;
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	enum ucode_state ret;
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	u32 eax;
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	if (!container)
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		return -EINVAL;
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#ifdef CONFIG_X86_32
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	get_bsp_sig();
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	cont = (unsigned long)container;
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#else
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	/*
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	 * We need the physical address of the container for both bitness since
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	 * boot_params.hdr.ramdisk_image is a physical address.
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	 */
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	cont = __pa(container);
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#endif
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	/*
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	 * Take into account the fact that the ramdisk might get relocated and
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	 * therefore we need to recompute the container's position in virtual
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	 * memory space.
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	 */
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	if (relocated_ramdisk)
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		container = (u8 *)(__va(relocated_ramdisk) +
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			     (cont - boot_params.hdr.ramdisk_image));
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	if (ucode_new_rev)
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		pr_info("microcode: updated early to new patch_level=0x%08x\n",
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			ucode_new_rev);
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	eax   = cpuid_eax(0x00000001);
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	eax   = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
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	ret = load_microcode_amd(eax, container, container_size);
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	if (ret != UCODE_OK)
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		return -EINVAL;
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	/*
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	 * This will be freed any msec now, stash patches for the current
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	 * family and switch to patch cache for cpu hotplug, etc later.
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	 */
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	container = NULL;
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	container_size = 0;
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	return 0;
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}
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