126ae9adc1
The default cache operations for ARM64 were changed during 3.15. To use coherent operations a "dma-coherent" device tree property is required. If that property is not present in the device tree node then the non-coherent operations are assigned for the device. Add support to the ccp driver to assign the AXI DMA cache settings based on whether the "dma-coherent" property is present in the device node. If present, use settings that work with the caches. If not present, use settings that do not look at the caches. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> |
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| .. | ||
| amd-ccp.txt | ||
| atmel-crypto.txt | ||
| fsl-dcp.txt | ||
| fsl-imx-sahara.txt | ||
| fsl-sec2.txt | ||
| fsl-sec4.txt | ||
| fsl-sec6.txt | ||
| mv_cesa.txt | ||
| omap-aes.txt | ||
| omap-des.txt | ||
| omap-sham.txt | ||
| picochip-spacc.txt | ||
| qcom-qce.txt | ||
| samsung-sss.txt | ||