c24b31147a
Merge irq-pxa168 and irq-mmp2. And support device tree also. Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, base irq starts from NR_IRQS_LEGACY. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
239 lines
7.4 KiB
C
239 lines
7.4 KiB
C
#ifndef __ASM_MACH_IRQS_H
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#define __ASM_MACH_IRQS_H
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/*
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* Interrupt numbers for PXA168
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*/
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#define IRQ_PXA168_NONE (-1)
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#define IRQ_PXA168_SSP4 0
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#define IRQ_PXA168_SSP3 1
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#define IRQ_PXA168_SSP2 2
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#define IRQ_PXA168_SSP1 3
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#define IRQ_PXA168_PMIC_INT 4
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#define IRQ_PXA168_RTC_INT 5
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#define IRQ_PXA168_RTC_ALARM 6
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#define IRQ_PXA168_TWSI0 7
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#define IRQ_PXA168_GPU 8
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#define IRQ_PXA168_KEYPAD 9
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#define IRQ_PXA168_ONEWIRE 12
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#define IRQ_PXA168_TIMER1 13
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#define IRQ_PXA168_TIMER2 14
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#define IRQ_PXA168_TIMER3 15
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#define IRQ_PXA168_CMU 16
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#define IRQ_PXA168_SSP5 17
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#define IRQ_PXA168_MSP_WAKEUP 19
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#define IRQ_PXA168_CF_WAKEUP 20
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#define IRQ_PXA168_XD_WAKEUP 21
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#define IRQ_PXA168_MFU 22
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#define IRQ_PXA168_MSP 23
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#define IRQ_PXA168_CF 24
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#define IRQ_PXA168_XD 25
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#define IRQ_PXA168_DDR_INT 26
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#define IRQ_PXA168_UART1 27
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#define IRQ_PXA168_UART2 28
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#define IRQ_PXA168_UART3 29
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#define IRQ_PXA168_WDT 35
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#define IRQ_PXA168_MAIN_PMU 36
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#define IRQ_PXA168_FRQ_CHANGE 38
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#define IRQ_PXA168_SDH1 39
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#define IRQ_PXA168_SDH2 40
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#define IRQ_PXA168_LCD 41
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#define IRQ_PXA168_CI 42
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#define IRQ_PXA168_USB1 44
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#define IRQ_PXA168_NAND 45
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#define IRQ_PXA168_HIFI_DMA 46
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#define IRQ_PXA168_DMA_INT0 47
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#define IRQ_PXA168_DMA_INT1 48
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#define IRQ_PXA168_GPIOX 49
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#define IRQ_PXA168_USB2 51
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#define IRQ_PXA168_AC97 57
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#define IRQ_PXA168_TWSI1 58
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#define IRQ_PXA168_AP_PMU 60
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#define IRQ_PXA168_SM_INT 63
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/*
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* Interrupt numbers for PXA910
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*/
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#define IRQ_PXA910_NONE (-1)
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#define IRQ_PXA910_AIRQ 0
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#define IRQ_PXA910_SSP3 1
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#define IRQ_PXA910_SSP2 2
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#define IRQ_PXA910_SSP1 3
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#define IRQ_PXA910_PMIC_INT 4
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#define IRQ_PXA910_RTC_INT 5
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#define IRQ_PXA910_RTC_ALARM 6
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#define IRQ_PXA910_TWSI0 7
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#define IRQ_PXA910_GPU 8
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#define IRQ_PXA910_KEYPAD 9
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#define IRQ_PXA910_ROTARY 10
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#define IRQ_PXA910_TRACKBALL 11
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#define IRQ_PXA910_ONEWIRE 12
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#define IRQ_PXA910_AP1_TIMER1 13
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#define IRQ_PXA910_AP1_TIMER2 14
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#define IRQ_PXA910_AP1_TIMER3 15
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#define IRQ_PXA910_IPC_AP0 16
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#define IRQ_PXA910_IPC_AP1 17
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#define IRQ_PXA910_IPC_AP2 18
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#define IRQ_PXA910_IPC_AP3 19
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#define IRQ_PXA910_IPC_AP4 20
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#define IRQ_PXA910_IPC_CP0 21
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#define IRQ_PXA910_IPC_CP1 22
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#define IRQ_PXA910_IPC_CP2 23
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#define IRQ_PXA910_IPC_CP3 24
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#define IRQ_PXA910_IPC_CP4 25
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#define IRQ_PXA910_L2_DDR 26
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#define IRQ_PXA910_UART2 27
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#define IRQ_PXA910_UART3 28
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#define IRQ_PXA910_AP2_TIMER1 29
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#define IRQ_PXA910_AP2_TIMER2 30
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#define IRQ_PXA910_CP2_TIMER1 31
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#define IRQ_PXA910_CP2_TIMER2 32
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#define IRQ_PXA910_CP2_TIMER3 33
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#define IRQ_PXA910_GSSP 34
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#define IRQ_PXA910_CP2_WDT 35
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#define IRQ_PXA910_MAIN_PMU 36
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#define IRQ_PXA910_CP_FREQ_CHG 37
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#define IRQ_PXA910_AP_FREQ_CHG 38
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#define IRQ_PXA910_MMC 39
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#define IRQ_PXA910_AEU 40
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#define IRQ_PXA910_LCD 41
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#define IRQ_PXA910_CCIC 42
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#define IRQ_PXA910_IRE 43
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#define IRQ_PXA910_USB1 44
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#define IRQ_PXA910_NAND 45
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#define IRQ_PXA910_HIFI_DMA 46
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#define IRQ_PXA910_DMA_INT0 47
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#define IRQ_PXA910_DMA_INT1 48
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#define IRQ_PXA910_AP_GPIO 49
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#define IRQ_PXA910_AP2_TIMER3 50
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#define IRQ_PXA910_USB2 51
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#define IRQ_PXA910_TWSI1 54
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#define IRQ_PXA910_CP_GPIO 55
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#define IRQ_PXA910_UART1 59 /* Slow UART */
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#define IRQ_PXA910_AP_PMU 60
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#define IRQ_PXA910_SM_INT 63 /* from PinMux */
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/*
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* Interrupt numbers for MMP2
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*/
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#define IRQ_MMP2_NONE (-1)
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#define IRQ_MMP2_SSP1 0
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#define IRQ_MMP2_SSP2 1
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#define IRQ_MMP2_SSPA1 2
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#define IRQ_MMP2_SSPA2 3
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#define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */
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#define IRQ_MMP2_RTC_MUX 5
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#define IRQ_MMP2_TWSI1 7
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#define IRQ_MMP2_GPU 8
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#define IRQ_MMP2_KEYPAD_MUX 9
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#define IRQ_MMP2_ROTARY 10
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#define IRQ_MMP2_TRACKBALL 11
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#define IRQ_MMP2_ONEWIRE 12
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#define IRQ_MMP2_TIMER1 13
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#define IRQ_MMP2_TIMER2 14
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#define IRQ_MMP2_TIMER3 15
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#define IRQ_MMP2_RIPC 16
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#define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */
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#define IRQ_MMP2_HDMI 19
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#define IRQ_MMP2_SSP3 20
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#define IRQ_MMP2_SSP4 21
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#define IRQ_MMP2_USB_HS1 22
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#define IRQ_MMP2_USB_HS2 23
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#define IRQ_MMP2_UART3 24
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#define IRQ_MMP2_UART1 27
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#define IRQ_MMP2_UART2 28
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#define IRQ_MMP2_MIPI_DSI 29
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#define IRQ_MMP2_CI2 30
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#define IRQ_MMP2_PMU_TIMER1 31
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#define IRQ_MMP2_PMU_TIMER2 32
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#define IRQ_MMP2_PMU_TIMER3 33
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#define IRQ_MMP2_USB_FS 34
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#define IRQ_MMP2_MISC_MUX 35
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#define IRQ_MMP2_WDT1 36
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#define IRQ_MMP2_NAND_DMA 37
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#define IRQ_MMP2_USIM 38
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#define IRQ_MMP2_MMC 39
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#define IRQ_MMP2_WTM 40
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#define IRQ_MMP2_LCD 41
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#define IRQ_MMP2_CI 42
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#define IRQ_MMP2_IRE 43
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#define IRQ_MMP2_USB_OTG 44
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#define IRQ_MMP2_NAND 45
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#define IRQ_MMP2_UART4 46
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#define IRQ_MMP2_DMA_FIQ 47
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#define IRQ_MMP2_DMA_RIQ 48
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#define IRQ_MMP2_GPIO 49
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#define IRQ_MMP2_MIPI_HSI1_MUX 51
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#define IRQ_MMP2_MMC2 52
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#define IRQ_MMP2_MMC3 53
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#define IRQ_MMP2_MMC4 54
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#define IRQ_MMP2_MIPI_HSI0_MUX 55
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#define IRQ_MMP2_MSP 58
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#define IRQ_MMP2_MIPI_SLIM_DMA 59
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#define IRQ_MMP2_PJ4_FREQ_CHG 60
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#define IRQ_MMP2_MIPI_SLIM 62
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#define IRQ_MMP2_SM 63
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#define IRQ_MMP2_MUX_BASE 64
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/* secondary interrupt of INT #4 */
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#define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE)
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#define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0)
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#define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1)
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/* secondary interrupt of INT #5 */
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#define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2)
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#define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0)
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#define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1)
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/* secondary interrupt of INT #9 */
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#define IRQ_MMP2_KEYPAD_BASE (IRQ_MMP2_RTC_BASE + 2)
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#define IRQ_MMP2_KPC (IRQ_MMP2_KEYPAD_BASE + 0)
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#define IRQ_MMP2_ROTORY (IRQ_MMP2_KEYPAD_BASE + 1)
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#define IRQ_MMP2_TBALL (IRQ_MMP2_KEYPAD_BASE + 2)
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/* secondary interrupt of INT #17 */
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#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_KEYPAD_BASE + 3)
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#define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0)
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#define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1)
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#define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2)
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#define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3)
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#define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4)
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/* secondary interrupt of INT #35 */
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#define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5)
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#define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0)
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#define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1)
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#define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2)
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#define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3)
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#define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4)
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#define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5)
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#define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6)
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#define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7)
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#define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9)
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#define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10)
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#define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11)
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#define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12)
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#define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13)
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#define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14)
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/* secondary interrupt of INT #51 */
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#define IRQ_MMP2_MIPI_HSI1_BASE (IRQ_MMP2_MISC_BASE + 15)
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#define IRQ_MMP2_HSI1_CAWAKE (IRQ_MMP2_MIPI_HSI1_BASE + 0)
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#define IRQ_MMP2_MIPI_HSI_INT1 (IRQ_MMP2_MIPI_HSI1_BASE + 1)
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/* secondary interrupt of INT #55 */
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#define IRQ_MMP2_MIPI_HSI0_BASE (IRQ_MMP2_MIPI_HSI1_BASE + 2)
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#define IRQ_MMP2_HSI0_CAWAKE (IRQ_MMP2_MIPI_HSI0_BASE + 0)
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#define IRQ_MMP2_MIPI_HSI_INT0 (IRQ_MMP2_MIPI_HSI0_BASE + 1)
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#define IRQ_MMP2_MUX_END (IRQ_MMP2_MIPI_HSI0_BASE + 2)
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#define IRQ_GPIO_START 128
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#define MMP_NR_BUILTIN_GPIO 192
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#define MMP_GPIO_TO_IRQ(gpio) (IRQ_GPIO_START + (gpio))
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#define IRQ_BOARD_START (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO)
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#define MMP_NR_IRQS IRQ_BOARD_START
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#endif /* __ASM_MACH_IRQS_H */
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