35bcaf00de
This patch adds devicetree support CCM module for i.MX21 CPUs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
80 lines
2.4 KiB
C
80 lines
2.4 KiB
C
/*
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* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX21_H
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#define __DT_BINDINGS_CLOCK_IMX21_H
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#define IMX21_CLK_DUMMY 0
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#define IMX21_CLK_CKIL 1
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#define IMX21_CLK_CKIH 2
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#define IMX21_CLK_FPM 3
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#define IMX21_CLK_CKIH_DIV1P5 4
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#define IMX21_CLK_MPLL_GATE 5
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#define IMX21_CLK_SPLL_GATE 6
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#define IMX21_CLK_FPM_GATE 7
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#define IMX21_CLK_CKIH_GATE 8
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#define IMX21_CLK_MPLL_OSC_SEL 9
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#define IMX21_CLK_IPG 10
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#define IMX21_CLK_HCLK 11
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#define IMX21_CLK_MPLL_SEL 12
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#define IMX21_CLK_SPLL_SEL 13
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#define IMX21_CLK_SSI1_SEL 14
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#define IMX21_CLK_SSI2_SEL 15
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#define IMX21_CLK_USB_DIV 16
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#define IMX21_CLK_FCLK 17
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#define IMX21_CLK_MPLL 18
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#define IMX21_CLK_SPLL 19
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#define IMX21_CLK_NFC_DIV 20
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#define IMX21_CLK_SSI1_DIV 21
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#define IMX21_CLK_SSI2_DIV 22
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#define IMX21_CLK_PER1 23
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#define IMX21_CLK_PER2 24
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#define IMX21_CLK_PER3 25
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#define IMX21_CLK_PER4 26
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#define IMX21_CLK_UART1_IPG_GATE 27
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#define IMX21_CLK_UART2_IPG_GATE 28
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#define IMX21_CLK_UART3_IPG_GATE 29
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#define IMX21_CLK_UART4_IPG_GATE 30
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#define IMX21_CLK_CSPI1_IPG_GATE 31
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#define IMX21_CLK_CSPI2_IPG_GATE 32
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#define IMX21_CLK_SSI1_GATE 33
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#define IMX21_CLK_SSI2_GATE 34
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#define IMX21_CLK_SDHC1_IPG_GATE 35
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#define IMX21_CLK_SDHC2_IPG_GATE 36
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#define IMX21_CLK_GPIO_GATE 37
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#define IMX21_CLK_I2C_GATE 38
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#define IMX21_CLK_DMA_GATE 39
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#define IMX21_CLK_USB_GATE 40
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#define IMX21_CLK_EMMA_GATE 41
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#define IMX21_CLK_SSI2_BAUD_GATE 42
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#define IMX21_CLK_SSI1_BAUD_GATE 43
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#define IMX21_CLK_LCDC_IPG_GATE 44
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#define IMX21_CLK_NFC_GATE 45
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#define IMX21_CLK_LCDC_HCLK_GATE 46
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#define IMX21_CLK_PER4_GATE 47
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#define IMX21_CLK_BMI_GATE 48
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#define IMX21_CLK_USB_HCLK_GATE 49
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#define IMX21_CLK_SLCDC_GATE 50
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#define IMX21_CLK_SLCDC_HCLK_GATE 51
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#define IMX21_CLK_EMMA_HCLK_GATE 52
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#define IMX21_CLK_BROM_GATE 53
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#define IMX21_CLK_DMA_HCLK_GATE 54
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#define IMX21_CLK_CSI_HCLK_GATE 55
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#define IMX21_CLK_CSPI3_IPG_GATE 56
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#define IMX21_CLK_WDOG_GATE 57
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#define IMX21_CLK_GPT1_IPG_GATE 58
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#define IMX21_CLK_GPT2_IPG_GATE 59
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#define IMX21_CLK_GPT3_IPG_GATE 60
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#define IMX21_CLK_PWM_IPG_GATE 61
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#define IMX21_CLK_RTC_GATE 62
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#define IMX21_CLK_KPP_GATE 63
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#define IMX21_CLK_OWIRE_GATE 64
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#define IMX21_CLK_MAX 65
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#endif
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