bac3fcfad5
mxc_gpio_mode checks for invalid pins and so it returns zero for success, -EINVAL for invalid pins. While at it, remove definitions of GPIO_PORT_MAX removed as they are unused now. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
103 lines
3.5 KiB
C
103 lines
3.5 KiB
C
/*
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* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
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* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __MACH_IOMUX_V1_H__
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#define __MACH_IOMUX_V1_H__
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/*
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* GPIO Module and I/O Multiplexer
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* x = 0..3 for reg_A, reg_B, reg_C, reg_D
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*/
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#define MXC_DDIR(x) (0x00 + ((x) << 8))
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#define MXC_OCR1(x) (0x04 + ((x) << 8))
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#define MXC_OCR2(x) (0x08 + ((x) << 8))
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#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
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#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
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#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
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#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
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#define MXC_DR(x) (0x1c + ((x) << 8))
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#define MXC_GIUS(x) (0x20 + ((x) << 8))
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#define MXC_SSR(x) (0x24 + ((x) << 8))
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#define MXC_ICR1(x) (0x28 + ((x) << 8))
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#define MXC_ICR2(x) (0x2c + ((x) << 8))
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#define MXC_IMR(x) (0x30 + ((x) << 8))
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#define MXC_ISR(x) (0x34 + ((x) << 8))
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#define MXC_GPR(x) (0x38 + ((x) << 8))
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#define MXC_SWR(x) (0x3c + ((x) << 8))
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#define MXC_PUEN(x) (0x40 + ((x) << 8))
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#define MX1_NUM_GPIO_PORT 4
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#define MX21_NUM_GPIO_PORT 6
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#define MX27_NUM_GPIO_PORT 6
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#define GPIO_PIN_MASK 0x1f
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#define GPIO_PORT_SHIFT 5
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#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
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#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
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#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
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#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
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#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
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#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
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#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
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#define GPIO_OUT (1 << 8)
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#define GPIO_IN (0 << 8)
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#define GPIO_PUEN (1 << 9)
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#define GPIO_PF (1 << 10)
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#define GPIO_AF (1 << 11)
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#define GPIO_OCR_SHIFT 12
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#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
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#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
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#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
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#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
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#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
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#define GPIO_AOUT_SHIFT 14
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#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
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#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
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#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
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#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
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#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
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#define GPIO_BOUT_SHIFT 16
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#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
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#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
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#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
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#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
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#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
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/* decode irq number to use with IMR(x), ISR(x) and friends */
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#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
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#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
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#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
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#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
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#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
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#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
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#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
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extern int mxc_gpio_mode(int gpio_mode);
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extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
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const char *label);
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extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
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#endif /* __MACH_IOMUX_V1_H__ */
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