426fcd2a35
This is the fix for proper reboot of Realview ARM1176PB board when issuing the reboot command. Setting the eighth bit of control register SYS_RESETCTL to 1 to force a soft reset. arch_reset() is modified for realview machines to call machine specific reset function pointers. Signed-off-by: Philby John <pjohn@in.mvista.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
96 lines
4.3 KiB
C
96 lines
4.3 KiB
C
/*
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* arch/arm/mach-realview/include/mach/board-pb11mp.h
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*
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* Copyright (C) 2008 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_BOARD_PB11MP_H
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#define __ASM_ARCH_BOARD_PB11MP_H
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#include <mach/platform.h>
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/*
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* Peripheral addresses
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*/
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#define REALVIEW_PB11MP_UART0_BASE 0x10009000 /* UART 0 */
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#define REALVIEW_PB11MP_UART1_BASE 0x1000A000 /* UART 1 */
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#define REALVIEW_PB11MP_UART2_BASE 0x1000B000 /* UART 2 */
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#define REALVIEW_PB11MP_UART3_BASE 0x1000C000 /* UART 3 */
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#define REALVIEW_PB11MP_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
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#define REALVIEW_PB11MP_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
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#define REALVIEW_PB11MP_WATCHDOG_BASE 0x10010000 /* watchdog interface */
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#define REALVIEW_PB11MP_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
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#define REALVIEW_PB11MP_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
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#define REALVIEW_PB11MP_GPIO0_BASE 0x10013000 /* GPIO port 0 */
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#define REALVIEW_PB11MP_RTC_BASE 0x10017000 /* Real Time Clock */
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#define REALVIEW_PB11MP_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
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#define REALVIEW_PB11MP_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
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#define REALVIEW_PB11MP_SCTL_BASE 0x1001A000 /* System Controller */
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#define REALVIEW_PB11MP_CLCD_BASE 0x10020000 /* CLCD */
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#define REALVIEW_PB11MP_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
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#define REALVIEW_PB11MP_DMC_BASE 0x100E0000 /* DMC configuration */
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#define REALVIEW_PB11MP_SMC_BASE 0x100E1000 /* SMC configuration */
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#define REALVIEW_PB11MP_CAN_BASE 0x100E2000 /* CAN bus */
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#define REALVIEW_PB11MP_CF_BASE 0x18000000 /* Compact flash */
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#define REALVIEW_PB11MP_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */
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#define REALVIEW_PB11MP_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
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#define REALVIEW_PB11MP_FLASH0_BASE 0x40000000
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#define REALVIEW_PB11MP_FLASH0_SIZE SZ_64M
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#define REALVIEW_PB11MP_FLASH1_BASE 0x44000000
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#define REALVIEW_PB11MP_FLASH1_SIZE SZ_64M
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#define REALVIEW_PB11MP_ETH_BASE 0x4E000000 /* Ethernet */
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#define REALVIEW_PB11MP_USB_BASE 0x4F000000 /* USB */
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#define REALVIEW_PB11MP_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
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#define REALVIEW_PB11MP_LT_BASE 0xC0000000 /* Logic Tile expansion */
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#define REALVIEW_PB11MP_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
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#define REALVIEW_PB11MP_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
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#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74
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/*
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* PB11MPCore PCI regions
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*/
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#define REALVIEW_PB11MP_PCI_BASE 0x90040000 /* PCI-X Unit base */
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#define REALVIEW_PB11MP_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
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#define REALVIEW_PB11MP_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
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#define REALVIEW_PB11MP_PCI_BASE_SIZE 0x10000 /* 16 Kb */
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#define REALVIEW_PB11MP_PCI_IO_SIZE 0x1000 /* 4 Kb */
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#define REALVIEW_PB11MP_PCI_MEM_SIZE 0x20000000 /* 512 MB */
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/*
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* Testchip peripheral and fpga gic regions
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*/
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#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
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#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */
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#define REALVIEW_TC11MP_TWD_BASE 0x1F000600
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#define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */
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#define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */
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/*
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* Values for REALVIEW_SYS_RESET_CTRL
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*/
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#define REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGCLR 0x01
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#define REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGINIT 0x02
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#define REALVIEW_PB11MP_SYS_CTRL_RESET_DLLRESET 0x03
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#define REALVIEW_PB11MP_SYS_CTRL_RESET_PLLRESET 0x04
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#define REALVIEW_PB11MP_SYS_CTRL_RESET_POR 0x05
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#define REALVIEW_PB11MP_SYS_CTRL_RESET_DoC 0x06
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#define REALVIEW_PB11MP_SYS_CTRL_LED (1 << 0)
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#endif /* __ASM_ARCH_BOARD_PB11MP_H */
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