The basic GPIO controllers may be found in various on-board FPGA and ASIC solutions that are used to control board's switches, LEDs, chip-selects, Ethernet/USB PHY power, etc. These controllers may not provide any means of pin setup (in/out/open drain). The driver supports: - 8/16/32/64 bits registers; - GPIO controllers with clear/set registers; - GPIO controllers with a single "data" register; - Big endian bits/GPIOs ordering (mostly used on PowerPC). Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com> Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: David Brownell <david-b@pacbell.net> Cc: Samuel Ortiz <sameo@linux.intel.com>, Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
		
			
				
	
	
		
			297 lines
		
	
	
	
		
			8 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			297 lines
		
	
	
	
		
			8 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Driver for basic memory-mapped GPIO controllers.
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 *
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 * Copyright 2008 MontaVista Software, Inc.
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 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
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 *
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 * This program is free software; you can redistribute  it and/or modify it
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 * under  the terms of  the GNU General  Public License as published by the
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 * Free Software Foundation;  either version 2 of the  License, or (at your
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 * option) any later version.
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 *
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 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
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 * ...``                                                         ```````..
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 * ..The simplest form of a GPIO controller that the driver supports is``
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 *  `.just a single "data" register, where GPIO state can be read and/or `
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 *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
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 *        `````````
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                                    ___
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_/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
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__________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
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o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
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                                                 `....trivial..'~`.```.```
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 *                                                    ```````
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 *  .```````~~~~`..`.``.``.
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 * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
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 * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
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 *  . register the device with -be`. .with a pair of set/clear-bit registers ,
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 *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
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 *     ``.`.``...```                  ```.. output pins are also supported.`
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 *                        ^^             `````.`````````.,``~``~``~~``````
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 *                                                   .                  ^^
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 *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
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 * .. The expectation is that in at least some cases .    ,-~~~-,
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 *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
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 *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
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 *  ..````````......```````````                             \o_
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 *                                                           |
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 *                              ^^                          / \
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 *
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 *           ...`````~~`.....``.`..........``````.`.``.```........``.
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 *            `  8, 16, 32 and 64 bits registers are supported, and``.
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 *            . the number of GPIOs is determined by the width of   ~
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 *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
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 *               `.......````.```
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 */
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#include <linux/init.h>
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/log2.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/mod_devicetable.h>
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#include <linux/basic_mmio_gpio.h>
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struct bgpio_chip {
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	struct gpio_chip gc;
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	void __iomem *reg_dat;
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	void __iomem *reg_set;
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	void __iomem *reg_clr;
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	/* Number of bits (GPIOs): <register width> * 8. */
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	int bits;
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	/*
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	 * Some GPIO controllers work with the big-endian bits notation,
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	 * e.g. in a 8-bits register, GPIO7 is the least significant bit.
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	 */
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	int big_endian_bits;
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	/*
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	 * Used to lock bgpio_chip->data. Also, this is needed to keep
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	 * shadowed and real data registers writes together.
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	 */
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	spinlock_t lock;
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	/* Shadowed data register to clear/set bits safely. */
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	unsigned long data;
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};
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static struct bgpio_chip *to_bgpio_chip(struct gpio_chip *gc)
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{
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	return container_of(gc, struct bgpio_chip, gc);
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}
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static unsigned long bgpio_in(struct bgpio_chip *bgc)
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{
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	switch (bgc->bits) {
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	case 8:
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		return __raw_readb(bgc->reg_dat);
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	case 16:
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		return __raw_readw(bgc->reg_dat);
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	case 32:
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		return __raw_readl(bgc->reg_dat);
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#if BITS_PER_LONG >= 64
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	case 64:
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		return __raw_readq(bgc->reg_dat);
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#endif
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	}
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	return -EINVAL;
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}
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static void bgpio_out(struct bgpio_chip *bgc, void __iomem *reg,
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		      unsigned long data)
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{
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	switch (bgc->bits) {
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	case 8:
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		__raw_writeb(data, reg);
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		return;
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	case 16:
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		__raw_writew(data, reg);
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		return;
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	case 32:
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		__raw_writel(data, reg);
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		return;
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#if BITS_PER_LONG >= 64
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	case 64:
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		__raw_writeq(data, reg);
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		return;
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#endif
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	}
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}
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static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
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{
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	if (bgc->big_endian_bits)
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		return 1 << (bgc->bits - 1 - pin);
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	else
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		return 1 << pin;
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}
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static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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	struct bgpio_chip *bgc = to_bgpio_chip(gc);
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	return bgpio_in(bgc) & bgpio_pin2mask(bgc, gpio);
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}
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static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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	struct bgpio_chip *bgc = to_bgpio_chip(gc);
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	unsigned long mask = bgpio_pin2mask(bgc, gpio);
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	unsigned long flags;
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	if (bgc->reg_set) {
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		if (val)
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			bgpio_out(bgc, bgc->reg_set, mask);
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		else
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			bgpio_out(bgc, bgc->reg_clr, mask);
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		return;
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	}
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	spin_lock_irqsave(&bgc->lock, flags);
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	if (val)
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		bgc->data |= mask;
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	else
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		bgc->data &= ~mask;
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	bgpio_out(bgc, bgc->reg_dat, bgc->data);
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	spin_unlock_irqrestore(&bgc->lock, flags);
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}
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static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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	return 0;
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}
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static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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	bgpio_set(gc, gpio, val);
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	return 0;
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}
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static int __devinit bgpio_probe(struct platform_device *pdev)
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{
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	const struct platform_device_id *platid = platform_get_device_id(pdev);
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	struct device *dev = &pdev->dev;
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	struct bgpio_pdata *pdata = dev_get_platdata(dev);
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	struct bgpio_chip *bgc;
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	struct resource *res_dat;
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	struct resource *res_set;
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	struct resource *res_clr;
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	resource_size_t dat_sz;
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	int bits;
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	int ret;
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	res_dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
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	if (!res_dat)
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		return -EINVAL;
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	dat_sz = resource_size(res_dat);
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	if (!is_power_of_2(dat_sz))
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		return -EINVAL;
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	bits = dat_sz * 8;
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	if (bits > BITS_PER_LONG)
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		return -EINVAL;
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	bgc = devm_kzalloc(dev, sizeof(*bgc), GFP_KERNEL);
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	if (!bgc)
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		return -ENOMEM;
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	bgc->reg_dat = devm_ioremap(dev, res_dat->start, dat_sz);
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	if (!bgc->reg_dat)
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		return -ENOMEM;
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	res_set = platform_get_resource_byname(pdev, IORESOURCE_MEM, "set");
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	res_clr = platform_get_resource_byname(pdev, IORESOURCE_MEM, "clr");
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	if (res_set && res_clr) {
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		if (resource_size(res_set) != resource_size(res_clr) ||
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				resource_size(res_set) != dat_sz)
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			return -EINVAL;
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		bgc->reg_set = devm_ioremap(dev, res_set->start, dat_sz);
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		bgc->reg_clr = devm_ioremap(dev, res_clr->start, dat_sz);
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		if (!bgc->reg_set || !bgc->reg_clr)
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			return -ENOMEM;
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	} else if (res_set || res_clr) {
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		return -EINVAL;
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	}
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	spin_lock_init(&bgc->lock);
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	bgc->bits = bits;
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	bgc->big_endian_bits = !strcmp(platid->name, "basic-mmio-gpio-be");
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	bgc->data = bgpio_in(bgc);
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	bgc->gc.ngpio = bits;
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	bgc->gc.direction_input = bgpio_dir_in;
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	bgc->gc.direction_output = bgpio_dir_out;
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	bgc->gc.get = bgpio_get;
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	bgc->gc.set = bgpio_set;
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	bgc->gc.dev = dev;
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	bgc->gc.label = dev_name(dev);
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	if (pdata)
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		bgc->gc.base = pdata->base;
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	else
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		bgc->gc.base = -1;
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	dev_set_drvdata(dev, bgc);
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	ret = gpiochip_add(&bgc->gc);
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	if (ret)
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		dev_err(dev, "gpiochip_add() failed: %d\n", ret);
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	return ret;
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}
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static int __devexit bgpio_remove(struct platform_device *pdev)
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{
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	struct bgpio_chip *bgc = dev_get_drvdata(&pdev->dev);
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	return gpiochip_remove(&bgc->gc);
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}
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static const struct platform_device_id bgpio_id_table[] = {
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	{ "basic-mmio-gpio", },
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	{ "basic-mmio-gpio-be", },
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	{},
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};
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MODULE_DEVICE_TABLE(platform, bgpio_id_table);
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static struct platform_driver bgpio_driver = {
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	.driver = {
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		.name = "basic-mmio-gpio",
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	},
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	.id_table = bgpio_id_table,
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	.probe = bgpio_probe,
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	.remove = __devexit_p(bgpio_remove),
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};
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static int __init bgpio_init(void)
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{
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	return platform_driver_register(&bgpio_driver);
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}
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module_init(bgpio_init);
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static void __exit bgpio_exit(void)
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{
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	platform_driver_unregister(&bgpio_driver);
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}
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module_exit(bgpio_exit);
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MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
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MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
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MODULE_LICENSE("GPL");
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