639da5ee37
Some platforms (like OMAP not to name it) are doing rather complicated hacks just to determine the base UART address to use. Let's give their addruart macro some slack by providing an extra work register which will allow for much needed cleanups. This is basically a no-op as this commit is only adding the extra argument to the macro but no one is using it yet. Signed-off-by: nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Kevin Hilman <khilman@ti.com>
62 lines
1.5 KiB
ArmAsm
62 lines
1.5 KiB
ArmAsm
/* arch/arm/mach-sa1100/include/mach/debug-macro.S
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*
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* Debugging macro include header
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*
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* Copyright (C) 1994-1999 Russell King
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <mach/hardware.h>
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.macro addruart, rp, rv, tmp
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mrc p15, 0, \rp, c1, c0
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tst \rp, #1 @ MMU enabled?
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moveq \rp, #0x80000000 @ physical base address
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movne \rp, #0xf8000000 @ virtual address
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@ We probe for the active serial port here, coherently with
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@ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
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@ We assume r1 can be clobbered.
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@ see if Ser3 is active
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add \rp, \rp, #0x00050000
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ldr \rv, [\rp, #UTCR3]
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tst \rv, #UTCR3_TXE
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@ if Ser3 is inactive, then try Ser1
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addeq \rp, \rp, #(0x00010000 - 0x00050000)
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ldreq \rv, [\rp, #UTCR3]
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tsteq \rv, #UTCR3_TXE
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@ if Ser1 is inactive, then try Ser2
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addeq \rp, \rp, #(0x00030000 - 0x00010000)
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ldreq \rv, [\rp, #UTCR3]
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tsteq \rv, #UTCR3_TXE
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@ clear top bits, and generate both phys and virt addresses
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lsl \rp, \rp, #8
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lsr \rp, \rp, #8
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orr \rv, \rp, #0xf8000000 @ virtual
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orr \rp, \rp, #0x80000000 @ physical
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.endm
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.macro senduart,rd,rx
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str \rd, [\rx, #UTDR]
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.endm
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.macro waituart,rd,rx
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1001: ldr \rd, [\rx, #UTSR1]
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tst \rd, #UTSR1_TNF
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beq 1001b
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.endm
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.macro busyuart,rd,rx
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1001: ldr \rd, [\rx, #UTSR1]
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tst \rd, #UTSR1_TBY
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bne 1001b
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.endm
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