74ac23a3e4
As SPI platform devices are consolidated to plat-samsung, some corresponding changes are required in the respective machine folder. Setup files are added for SPI GPIO configurations and platform data initialization. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
72 lines
1.8 KiB
C
72 lines
1.8 KiB
C
/* linux/arch/arm/mach-exynos4/setup-spi.c
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*
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* Copyright (C) 2011 Samsung Electronics Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <plat/gpio-cfg.h>
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#include <plat/s3c64xx-spi.h>
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#ifdef CONFIG_S3C64XX_DEV_SPI0
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struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
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.fifo_lvl_mask = 0x1ff,
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.rx_lvl_offset = 15,
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.high_speed = 1,
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.clk_from_cmu = true,
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.tx_st_done = 25,
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};
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int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
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{
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s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
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s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
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S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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#ifdef CONFIG_S3C64XX_DEV_SPI1
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struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 15,
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.high_speed = 1,
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.clk_from_cmu = true,
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.tx_st_done = 25,
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};
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int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
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{
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s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
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s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
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S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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#ifdef CONFIG_S3C64XX_DEV_SPI2
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struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 15,
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.high_speed = 1,
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.clk_from_cmu = true,
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.tx_st_done = 25,
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};
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int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
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{
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s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
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s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
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S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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