830145796a
The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has made for plaforms based on EXYNOS4 SoCs. But since upcoming Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most codes in current mach-exynos4, one mach-exynos directory will be used for them. This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos) but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to avoid changing in driver side. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
53 lines
1.7 KiB
C
53 lines
1.7 KiB
C
/* arch/arm/mach-exynos4/include/mach/regs-mct.h
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4 MCT configutation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_MCT_H
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#define __ASM_ARCH_REGS_MCT_H __FILE__
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#include <mach/map.h>
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#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
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#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
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#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
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#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
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#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
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#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
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#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
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#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
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#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
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#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
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#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
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#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
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#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
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#define EXYNOS4_MCT_L_MASK (0xffffff00)
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#define MCT_L_TCNTB_OFFSET (0x00)
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#define MCT_L_ICNTB_OFFSET (0x08)
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#define MCT_L_TCON_OFFSET (0x20)
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#define MCT_L_INT_CSTAT_OFFSET (0x30)
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#define MCT_L_INT_ENB_OFFSET (0x34)
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#define MCT_L_WSTAT_OFFSET (0x40)
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#define MCT_G_TCON_START (1 << 8)
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#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
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#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
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#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
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#define MCT_L_TCON_INT_START (1 << 1)
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#define MCT_L_TCON_TIMER_START (1 << 0)
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#endif /* __ASM_ARCH_REGS_MCT_H */
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