ppc has special instruction forms to efficiently load and store values
in non-native endianness.  These can be accessed via the arch-specific
{ld,st}_le{16,32}() inlines in arch/powerpc/include/asm/swab.h.
However, gcc is perfectly capable of generating the byte-reversing
load/store instructions when using the normal, generic cpu_to_le*() and
le*_to_cpu() functions eaning the arch-specific functions don't have much
point.
Worse the "le" in the names of the arch specific functions is now
misleading, because they always generate byte-reversing forms, but some
ppc machines can now run a little-endian kernel.
To start getting rid of the arch-specific forms, this patch removes them
from all the old Power Macintosh drivers, replacing them with the
generic byteswappers.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
		
	
			
		
			
				
	
	
		
			108 lines
		
	
	
	
		
			3.7 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			108 lines
		
	
	
	
		
			3.7 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Definitions for using the Apple Descriptor-Based DMA controller
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 * in Power Macintosh computers.
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 *
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 * Copyright (C) 1996 Paul Mackerras.
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 */
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#ifdef __KERNEL__
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#ifndef _ASM_DBDMA_H_
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#define _ASM_DBDMA_H_
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/*
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 * DBDMA control/status registers.  All little-endian.
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 */
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struct dbdma_regs {
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    unsigned int control;	/* lets you change bits in status */
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    unsigned int status;	/* DMA and device status bits (see below) */
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    unsigned int cmdptr_hi;	/* upper 32 bits of command address */
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    unsigned int cmdptr;	/* (lower 32 bits of) command address (phys) */
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    unsigned int intr_sel;	/* select interrupt condition bit */
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    unsigned int br_sel;	/* select branch condition bit */
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    unsigned int wait_sel;	/* select wait condition bit */
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    unsigned int xfer_mode;
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    unsigned int data2ptr_hi;
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    unsigned int data2ptr;
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    unsigned int res1;
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    unsigned int address_hi;
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    unsigned int br_addr_hi;
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    unsigned int res2[3];
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};
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/* Bits in control and status registers */
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#define RUN	0x8000
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#define PAUSE	0x4000
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#define FLUSH	0x2000
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#define WAKE	0x1000
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#define DEAD	0x0800
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#define ACTIVE	0x0400
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#define BT	0x0100
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#define DEVSTAT	0x00ff
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/*
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 * DBDMA command structure.  These fields are all little-endian!
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 */
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struct dbdma_cmd {
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	__le16 req_count;	/* requested byte transfer count */
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	__le16 command;		/* command word (has bit-fields) */
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	__le32 phy_addr;	/* physical data address */
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	__le32 cmd_dep;		/* command-dependent field */
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	__le16 res_count;	/* residual count after completion */
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	__le16 xfer_status;	/* transfer status */
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};
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/* DBDMA command values in command field */
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#define OUTPUT_MORE	0	/* transfer memory data to stream */
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#define OUTPUT_LAST	0x1000	/* ditto followed by end marker */
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#define INPUT_MORE	0x2000	/* transfer stream data to memory */
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#define INPUT_LAST	0x3000	/* ditto, expect end marker */
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#define STORE_WORD	0x4000	/* write word (4 bytes) to device reg */
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#define LOAD_WORD	0x5000	/* read word (4 bytes) from device reg */
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#define DBDMA_NOP	0x6000	/* do nothing */
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#define DBDMA_STOP	0x7000	/* suspend processing */
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/* Key values in command field */
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#define KEY_STREAM0	0	/* usual data stream */
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#define KEY_STREAM1	0x100	/* control/status stream */
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#define KEY_STREAM2	0x200	/* device-dependent stream */
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#define KEY_STREAM3	0x300	/* device-dependent stream */
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#define KEY_REGS	0x500	/* device register space */
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#define KEY_SYSTEM	0x600	/* system memory-mapped space */
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#define KEY_DEVICE	0x700	/* device memory-mapped space */
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/* Interrupt control values in command field */
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#define INTR_NEVER	0	/* don't interrupt */
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#define INTR_IFSET	0x10	/* intr if condition bit is 1 */
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#define INTR_IFCLR	0x20	/* intr if condition bit is 0 */
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#define INTR_ALWAYS	0x30	/* always interrupt */
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/* Branch control values in command field */
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#define BR_NEVER	0	/* don't branch */
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#define BR_IFSET	0x4	/* branch if condition bit is 1 */
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#define BR_IFCLR	0x8	/* branch if condition bit is 0 */
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#define BR_ALWAYS	0xc	/* always branch */
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/* Wait control values in command field */
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#define WAIT_NEVER	0	/* don't wait */
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#define WAIT_IFSET	1	/* wait if condition bit is 1 */
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#define WAIT_IFCLR	2	/* wait if condition bit is 0 */
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#define WAIT_ALWAYS	3	/* always wait */
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/* Align an address for a DBDMA command structure */
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#define DBDMA_ALIGN(x)	(((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
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			 & -sizeof(struct dbdma_cmd))
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/* Useful macros */
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#define DBDMA_DO_STOP(regs) do {				\
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	out_le32(&((regs)->control), (RUN|FLUSH)<<16);		\
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	while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH))	\
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		; \
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} while(0)
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#define DBDMA_DO_RESET(regs) do {				\
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	out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
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	while(in_le32(&((regs)->status)) & (RUN)) \
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		; \
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} while(0)
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#endif /* _ASM_DBDMA_H_ */
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#endif /* __KERNEL__ */
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