e7101c2ae2
Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7270/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
121 lines
2.5 KiB
C
121 lines
2.5 KiB
C
#ifndef BCM63XX_DEV_ENET_H_
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#define BCM63XX_DEV_ENET_H_
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#include <linux/if_ether.h>
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#include <linux/init.h>
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#include <bcm63xx_regs.h>
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/*
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* on board ethernet platform data
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*/
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struct bcm63xx_enet_platform_data {
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char mac_addr[ETH_ALEN];
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int has_phy;
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/* if has_phy, then set use_internal_phy */
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int use_internal_phy;
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/* or fill phy info to use an external one */
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int phy_id;
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int has_phy_interrupt;
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int phy_interrupt;
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/* if has_phy, use autonegociated pause parameters or force
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* them */
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int pause_auto;
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int pause_rx;
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int pause_tx;
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/* if !has_phy, set desired forced speed/duplex */
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int force_speed_100;
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int force_duplex_full;
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/* if !has_phy, set callback to perform mii device
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* init/remove */
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int (*mii_config)(struct net_device *dev, int probe,
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int (*mii_read)(struct net_device *dev,
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int phy_id, int reg),
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void (*mii_write)(struct net_device *dev,
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int phy_id, int reg, int val));
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/* DMA channel enable mask */
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u32 dma_chan_en_mask;
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/* DMA channel interrupt mask */
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u32 dma_chan_int_mask;
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/* DMA engine has internal SRAM */
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bool dma_has_sram;
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/* DMA channel register width */
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unsigned int dma_chan_width;
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/* DMA descriptor shift */
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unsigned int dma_desc_shift;
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};
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/*
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* on board ethernet switch platform data
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*/
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#define ENETSW_MAX_PORT 8
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#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
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#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
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#define ENETSW_RGMII_PORT0 4
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struct bcm63xx_enetsw_port {
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int used;
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int phy_id;
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int bypass_link;
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int force_speed;
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int force_duplex_full;
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const char *name;
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};
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struct bcm63xx_enetsw_platform_data {
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char mac_addr[ETH_ALEN];
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int num_ports;
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struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
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/* DMA channel enable mask */
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u32 dma_chan_en_mask;
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/* DMA channel interrupt mask */
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u32 dma_chan_int_mask;
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/* DMA channel register width */
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unsigned int dma_chan_width;
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/* DMA engine has internal SRAM */
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bool dma_has_sram;
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};
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int __init bcm63xx_enet_register(int unit,
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const struct bcm63xx_enet_platform_data *pd);
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int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
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enum bcm63xx_regs_enetdmac {
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ENETDMAC_CHANCFG,
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ENETDMAC_IR,
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ENETDMAC_IRMASK,
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ENETDMAC_MAXBURST,
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ENETDMAC_BUFALLOC,
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ENETDMAC_RSTART,
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ENETDMAC_FC,
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ENETDMAC_LEN,
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};
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static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
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{
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extern const unsigned long *bcm63xx_regs_enetdmac;
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return bcm63xx_regs_enetdmac[reg];
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}
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#endif /* ! BCM63XX_DEV_ENET_H_ */
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