d0776aff9a
Move cpu_resume() to the .text section where it belongs. Change the adr reference to sleep_save_sp to an explicit PC relative reference so sleep_save_sp itself can remain in .data. This helps prevent linker failure on large kernels, as the code in the .data section may be too far away to be in range for normal b/bl instructions. Reviewed-by: Nicolas Pitre <nico@linaro.org> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
162 lines
4.5 KiB
ArmAsm
162 lines
4.5 KiB
ArmAsm
#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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#include <asm/glue-cache.h>
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#include <asm/glue-proc.h>
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.text
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/*
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* Implementation of MPIDR hash algorithm through shifting
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* and OR'ing.
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*
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* @dst: register containing hash result
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* @rs0: register containing affinity level 0 bit shift
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* @rs1: register containing affinity level 1 bit shift
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* @rs2: register containing affinity level 2 bit shift
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* @mpidr: register containing MPIDR value
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* @mask: register containing MPIDR mask
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*
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* Pseudo C-code:
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*
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*u32 dst;
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*
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*compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
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* u32 aff0, aff1, aff2;
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* u32 mpidr_masked = mpidr & mask;
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* aff0 = mpidr_masked & 0xff;
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* aff1 = mpidr_masked & 0xff00;
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* aff2 = mpidr_masked & 0xff0000;
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* dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
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*}
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* Input registers: rs0, rs1, rs2, mpidr, mask
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* Output register: dst
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* Note: input and output registers must be disjoint register sets
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(eg: a macro instance with mpidr = r1 and dst = r1 is invalid)
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*/
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.macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
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and \mpidr, \mpidr, \mask @ mask out MPIDR bits
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and \dst, \mpidr, #0xff @ mask=aff0
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ARM( mov \dst, \dst, lsr \rs0 ) @ dst=aff0>>rs0
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THUMB( lsr \dst, \dst, \rs0 )
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and \mask, \mpidr, #0xff00 @ mask = aff1
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ARM( orr \dst, \dst, \mask, lsr \rs1 ) @ dst|=(aff1>>rs1)
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THUMB( lsr \mask, \mask, \rs1 )
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THUMB( orr \dst, \dst, \mask )
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and \mask, \mpidr, #0xff0000 @ mask = aff2
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ARM( orr \dst, \dst, \mask, lsr \rs2 ) @ dst|=(aff2>>rs2)
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THUMB( lsr \mask, \mask, \rs2 )
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THUMB( orr \dst, \dst, \mask )
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.endm
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/*
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* Save CPU state for a suspend. This saves the CPU general purpose
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* registers, and allocates space on the kernel stack to save the CPU
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* specific registers and some other data for resume.
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* r0 = suspend function arg0
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* r1 = suspend function
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* r2 = MPIDR value the resuming CPU will use
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*/
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ENTRY(__cpu_suspend)
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stmfd sp!, {r4 - r11, lr}
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#ifdef MULTI_CPU
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ldr r10, =processor
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ldr r4, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
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#else
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ldr r4, =cpu_suspend_size
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#endif
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mov r5, sp @ current virtual SP
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add r4, r4, #12 @ Space for pgd, virt sp, phys resume fn
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sub sp, sp, r4 @ allocate CPU state on stack
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ldr r3, =sleep_save_sp
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stmfd sp!, {r0, r1} @ save suspend func arg and pointer
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ldr r3, [r3, #SLEEP_SAVE_SP_VIRT]
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ALT_SMP(ldr r0, =mpidr_hash)
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ALT_UP_B(1f)
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/* This ldmia relies on the memory layout of the mpidr_hash struct */
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ldmia r0, {r1, r6-r8} @ r1 = mpidr mask (r6,r7,r8) = l[0,1,2] shifts
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compute_mpidr_hash r0, r6, r7, r8, r2, r1
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add r3, r3, r0, lsl #2
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1: mov r2, r5 @ virtual SP
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mov r1, r4 @ size of save block
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add r0, sp, #8 @ pointer to save block
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bl __cpu_suspend_save
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adr lr, BSYM(cpu_suspend_abort)
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ldmfd sp!, {r0, pc} @ call suspend fn
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ENDPROC(__cpu_suspend)
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.ltorg
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cpu_suspend_abort:
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ldmia sp!, {r1 - r3} @ pop phys pgd, virt SP, phys resume fn
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teq r0, #0
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moveq r0, #1 @ force non-zero value
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mov sp, r2
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ldmfd sp!, {r4 - r11, pc}
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ENDPROC(cpu_suspend_abort)
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/*
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* r0 = control register value
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*/
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.align 5
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.pushsection .idmap.text,"ax"
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ENTRY(cpu_resume_mmu)
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ldr r3, =cpu_resume_after_mmu
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instr_sync
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mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
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mrc p15, 0, r0, c0, c0, 0 @ read id reg
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instr_sync
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mov r0, r0
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mov r0, r0
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ret r3 @ jump to virtual address
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ENDPROC(cpu_resume_mmu)
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.popsection
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cpu_resume_after_mmu:
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bl cpu_init @ restore the und/abt/irq banked regs
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mov r0, #0 @ return zero on success
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ldmfd sp!, {r4 - r11, pc}
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ENDPROC(cpu_resume_after_mmu)
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.text
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.align
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ENTRY(cpu_resume)
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ARM_BE8(setend be) @ ensure we are in BE mode
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#ifdef CONFIG_ARM_VIRT_EXT
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bl __hyp_stub_install_secondary
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#endif
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safe_svcmode_maskall r1
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mov r1, #0
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ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
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ALT_UP_B(1f)
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adr r2, mpidr_hash_ptr
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ldr r3, [r2]
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add r2, r2, r3 @ r2 = struct mpidr_hash phys address
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/*
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* This ldmia relies on the memory layout of the mpidr_hash
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* struct mpidr_hash.
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*/
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ldmia r2, { r3-r6 } @ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts
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compute_mpidr_hash r1, r4, r5, r6, r0, r3
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1:
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adr r0, _sleep_save_sp
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ldr r2, [r0]
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add r0, r0, r2
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ldr r0, [r0, #SLEEP_SAVE_SP_PHYS]
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ldr r0, [r0, r1, lsl #2]
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@ load phys pgd, stack, resume fn
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ARM( ldmia r0!, {r1, sp, pc} )
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THUMB( ldmia r0!, {r1, r2, r3} )
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THUMB( mov sp, r2 )
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THUMB( bx r3 )
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ENDPROC(cpu_resume)
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.align 2
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_sleep_save_sp:
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.long sleep_save_sp - .
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mpidr_hash_ptr:
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.long mpidr_hash - . @ mpidr_hash struct offset
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.data
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.type sleep_save_sp, #object
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ENTRY(sleep_save_sp)
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.space SLEEP_SAVE_SP_SZ @ struct sleep_save_sp
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