591f3dc200
The assertion of the lock-bit in the hardware register is unreliable, because there are devices with quirks that will randomly set the bit. Do the assertion in software, only. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
407 lines
9.9 KiB
C
407 lines
9.9 KiB
C
/*
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Broadcom B43 wireless driver
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Common PHY routines
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Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
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Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
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Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
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Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
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Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
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Boston, MA 02110-1301, USA.
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*/
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#include "phy_common.h"
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#include "phy_g.h"
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#include "phy_a.h"
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#include "phy_n.h"
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#include "phy_lp.h"
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#include "b43.h"
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#include "main.h"
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int b43_phy_allocate(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &(dev->phy);
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int err;
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phy->ops = NULL;
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switch (phy->type) {
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case B43_PHYTYPE_A:
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phy->ops = &b43_phyops_a;
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break;
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case B43_PHYTYPE_G:
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phy->ops = &b43_phyops_g;
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break;
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case B43_PHYTYPE_N:
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#ifdef CONFIG_B43_NPHY
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phy->ops = &b43_phyops_n;
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#endif
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break;
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case B43_PHYTYPE_LP:
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#ifdef CONFIG_B43_PHY_LP
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phy->ops = &b43_phyops_lp;
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#endif
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break;
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}
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if (B43_WARN_ON(!phy->ops))
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return -ENODEV;
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err = phy->ops->allocate(dev);
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if (err)
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phy->ops = NULL;
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return err;
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}
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void b43_phy_free(struct b43_wldev *dev)
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{
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dev->phy.ops->free(dev);
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dev->phy.ops = NULL;
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}
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int b43_phy_init(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &dev->phy;
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const struct b43_phy_operations *ops = phy->ops;
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int err;
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phy->channel = ops->get_default_chan(dev);
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ops->software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
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err = ops->init(dev);
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if (err) {
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b43err(dev->wl, "PHY init failed\n");
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goto err_block_rf;
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}
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/* Make sure to switch hardware and firmware (SHM) to
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* the default channel. */
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err = b43_switch_channel(dev, ops->get_default_chan(dev));
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if (err) {
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b43err(dev->wl, "PHY init: Channel switch to default failed\n");
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goto err_phy_exit;
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}
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return 0;
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err_phy_exit:
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if (ops->exit)
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ops->exit(dev);
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err_block_rf:
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ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
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return err;
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}
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void b43_phy_exit(struct b43_wldev *dev)
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{
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const struct b43_phy_operations *ops = dev->phy.ops;
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ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
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if (ops->exit)
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ops->exit(dev);
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}
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bool b43_has_hardware_pctl(struct b43_wldev *dev)
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{
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if (!dev->phy.hardware_power_control)
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return 0;
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if (!dev->phy.ops->supports_hwpctl)
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return 0;
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return dev->phy.ops->supports_hwpctl(dev);
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}
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void b43_radio_lock(struct b43_wldev *dev)
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{
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u32 macctl;
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#if B43_DEBUG
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B43_WARN_ON(dev->phy.radio_locked);
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dev->phy.radio_locked = 1;
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#endif
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macctl = b43_read32(dev, B43_MMIO_MACCTL);
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macctl |= B43_MACCTL_RADIOLOCK;
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b43_write32(dev, B43_MMIO_MACCTL, macctl);
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/* Commit the write and wait for the firmware
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* to finish any radio register access. */
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b43_read32(dev, B43_MMIO_MACCTL);
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udelay(10);
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}
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void b43_radio_unlock(struct b43_wldev *dev)
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{
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u32 macctl;
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#if B43_DEBUG
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B43_WARN_ON(!dev->phy.radio_locked);
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dev->phy.radio_locked = 0;
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#endif
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/* Commit any write */
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b43_read16(dev, B43_MMIO_PHY_VER);
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/* unlock */
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macctl = b43_read32(dev, B43_MMIO_MACCTL);
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macctl &= ~B43_MACCTL_RADIOLOCK;
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b43_write32(dev, B43_MMIO_MACCTL, macctl);
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}
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void b43_phy_lock(struct b43_wldev *dev)
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{
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#if B43_DEBUG
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B43_WARN_ON(dev->phy.phy_locked);
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dev->phy.phy_locked = 1;
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#endif
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B43_WARN_ON(dev->dev->id.revision < 3);
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if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
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b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
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}
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void b43_phy_unlock(struct b43_wldev *dev)
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{
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#if B43_DEBUG
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B43_WARN_ON(!dev->phy.phy_locked);
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dev->phy.phy_locked = 0;
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#endif
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B43_WARN_ON(dev->dev->id.revision < 3);
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if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
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b43_power_saving_ctl_bits(dev, 0);
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}
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static inline void assert_mac_suspended(struct b43_wldev *dev)
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{
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if (!B43_DEBUG)
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return;
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if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
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(dev->mac_suspended <= 0)) {
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b43dbg(dev->wl, "PHY/RADIO register access with "
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"enabled MAC.\n");
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dump_stack();
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}
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}
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u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
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{
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assert_mac_suspended(dev);
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return dev->phy.ops->radio_read(dev, reg);
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}
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void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
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{
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assert_mac_suspended(dev);
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dev->phy.ops->radio_write(dev, reg, value);
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}
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void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
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{
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b43_radio_write16(dev, offset,
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b43_radio_read16(dev, offset) & mask);
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}
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void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
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{
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b43_radio_write16(dev, offset,
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b43_radio_read16(dev, offset) | set);
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}
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void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
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{
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b43_radio_write16(dev, offset,
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(b43_radio_read16(dev, offset) & mask) | set);
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}
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u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
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{
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assert_mac_suspended(dev);
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return dev->phy.ops->phy_read(dev, reg);
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}
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void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
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{
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assert_mac_suspended(dev);
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dev->phy.ops->phy_write(dev, reg, value);
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}
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void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
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{
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b43_phy_write(dev, offset,
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b43_phy_read(dev, offset) & mask);
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}
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void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
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{
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b43_phy_write(dev, offset,
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b43_phy_read(dev, offset) | set);
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}
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void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
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{
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b43_phy_write(dev, offset,
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(b43_phy_read(dev, offset) & mask) | set);
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}
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int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
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{
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struct b43_phy *phy = &(dev->phy);
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u16 channelcookie, savedcookie;
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int err;
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if (new_channel == B43_DEFAULT_CHANNEL)
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new_channel = phy->ops->get_default_chan(dev);
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/* First we set the channel radio code to prevent the
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* firmware from sending ghost packets.
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*/
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channelcookie = new_channel;
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if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
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channelcookie |= 0x100;
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//FIXME set 40Mhz flag if required
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savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
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b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
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/* Now try to switch the PHY hardware channel. */
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err = phy->ops->switch_channel(dev, new_channel);
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if (err)
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goto err_restore_cookie;
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dev->phy.channel = new_channel;
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/* Wait for the radio to tune to the channel and stabilize. */
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msleep(8);
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return 0;
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err_restore_cookie:
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b43_shm_write16(dev, B43_SHM_SHARED,
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B43_SHM_SH_CHAN, savedcookie);
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return err;
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}
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void b43_software_rfkill(struct b43_wldev *dev, enum rfkill_state state)
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{
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struct b43_phy *phy = &dev->phy;
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if (state == RFKILL_STATE_HARD_BLOCKED) {
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/* We cannot hardware-block the device */
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state = RFKILL_STATE_SOFT_BLOCKED;
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}
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b43_mac_suspend(dev);
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phy->ops->software_rfkill(dev, state);
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phy->radio_on = (state == RFKILL_STATE_UNBLOCKED);
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b43_mac_enable(dev);
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}
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/**
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* b43_phy_txpower_adjust_work - TX power workqueue.
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*
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* Workqueue for updating the TX power parameters in hardware.
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*/
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void b43_phy_txpower_adjust_work(struct work_struct *work)
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{
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struct b43_wl *wl = container_of(work, struct b43_wl,
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txpower_adjust_work);
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struct b43_wldev *dev;
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mutex_lock(&wl->mutex);
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dev = wl->current_dev;
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if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
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dev->phy.ops->adjust_txpower(dev);
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mutex_unlock(&wl->mutex);
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}
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/* Called with wl->irq_lock locked */
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void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
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{
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struct b43_phy *phy = &dev->phy;
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unsigned long now = jiffies;
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enum b43_txpwr_result result;
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if (!(flags & B43_TXPWR_IGNORE_TIME)) {
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/* Check if it's time for a TXpower check. */
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if (time_before(now, phy->next_txpwr_check_time))
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return; /* Not yet */
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}
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/* The next check will be needed in two seconds, or later. */
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phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
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if ((dev->dev->bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
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(dev->dev->bus->boardinfo.type == SSB_BOARD_BU4306))
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return; /* No software txpower adjustment needed */
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result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
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if (result == B43_TXPWR_RES_DONE)
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return; /* We are done. */
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B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
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B43_WARN_ON(phy->ops->adjust_txpower == NULL);
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/* We must adjust the transmission power in hardware.
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* Schedule b43_phy_txpower_adjust_work(). */
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queue_work(dev->wl->hw->workqueue, &dev->wl->txpower_adjust_work);
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}
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int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
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{
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const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
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unsigned int a, b, c, d;
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unsigned int average;
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u32 tmp;
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tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
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a = tmp & 0xFF;
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b = (tmp >> 8) & 0xFF;
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c = (tmp >> 16) & 0xFF;
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d = (tmp >> 24) & 0xFF;
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if (a == 0 || a == B43_TSSI_MAX ||
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b == 0 || b == B43_TSSI_MAX ||
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c == 0 || c == B43_TSSI_MAX ||
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d == 0 || d == B43_TSSI_MAX)
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return -ENOENT;
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/* The values are OK. Clear them. */
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tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
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(B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
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b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
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if (is_ofdm) {
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a = (a + 32) & 0x3F;
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b = (b + 32) & 0x3F;
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c = (c + 32) & 0x3F;
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d = (d + 32) & 0x3F;
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}
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/* Get the average of the values with 0.5 added to each value. */
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average = (a + b + c + d + 2) / 4;
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if (is_ofdm) {
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/* Adjust for CCK-boost */
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if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
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& B43_HF_CCKBOOST)
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average = (average >= 13) ? (average - 13) : 0;
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}
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return average;
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}
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void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
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{
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b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
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}
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