80 lines
1.5 KiB
C
80 lines
1.5 KiB
C
#ifndef EXCITE_FPGA_H_INCLUDED
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#define EXCITE_FPGA_H_INCLUDED
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/**
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* Address alignment of the individual FPGA bytes.
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* The address arrangement of the individual bytes of the FPGA is two
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* byte aligned at the embedded MK2 platform.
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*/
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#ifdef EXCITE_CCI_FPGA_MK2
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typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
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#else
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typedef unsigned char excite_cci_fpga_align_t;
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#endif
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/**
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* Size of Dual Ported RAM.
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*/
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#define EXCITE_DPR_SIZE 263
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/**
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* Size of Reserved Status Fields in Dual Ported RAM.
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*/
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#define EXCITE_DPR_STATUS_SIZE 7
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/**
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* FPGA.
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* Hardware register layout of the FPGA interface. The FPGA must accessed
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* byte wise solely.
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* @see EXCITE_CCI_DPR_MK2
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*/
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typedef struct excite_fpga {
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/**
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* Dual Ported RAM.
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*/
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excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
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/**
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* Status.
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*/
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excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
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#ifdef EXCITE_CCI_FPGA_MK2
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/**
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* RM9000 Interrupt.
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* Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
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*/
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excite_cci_fpga_align_t rm9k_int;
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#else
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/**
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* MK2 Interrupt.
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* Write access initiates interrupt at the ARM processor of the MK2.
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*/
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excite_cci_fpga_align_t mk2_int;
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excite_cci_fpga_align_t gap[0x1000-0x10f];
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/**
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* IRQ Source/Acknowledge.
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*/
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excite_cci_fpga_align_t rm9k_irq_src;
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/**
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* IRQ Mask.
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* Set bits enable the related interrupt.
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*/
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excite_cci_fpga_align_t rm9k_irq_mask;
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#endif
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} excite_fpga;
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#endif /* ndef EXCITE_FPGA_H_INCLUDED */
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