This clock drives the INTCA irqpin controller modules. Before, it was assumed enabled by the bootloader or reset state. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: devicetree@vger.kernel.org Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
		
			
				
	
	
		
			78 lines
		
	
	
	
		
			1.9 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			78 lines
		
	
	
	
		
			1.9 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright 2014 Ulrich Hecht
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 */
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#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
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#define __DT_BINDINGS_CLOCK_R8A7740_H__
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/* CPG */
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#define R8A7740_CLK_SYSTEM	0
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#define R8A7740_CLK_PLLC0	1
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#define R8A7740_CLK_PLLC1	2
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#define R8A7740_CLK_PLLC2	3
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#define R8A7740_CLK_R		4
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#define R8A7740_CLK_USB24S	5
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#define R8A7740_CLK_I		6
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#define R8A7740_CLK_ZG		7
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#define R8A7740_CLK_B		8
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#define R8A7740_CLK_M1		9
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#define R8A7740_CLK_HP		10
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#define R8A7740_CLK_HPP		11
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#define R8A7740_CLK_USBP	12
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#define R8A7740_CLK_S		13
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#define R8A7740_CLK_ZB		14
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#define R8A7740_CLK_M3		15
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#define R8A7740_CLK_CP		16
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/* MSTP1 */
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#define R8A7740_CLK_CEU21	28
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#define R8A7740_CLK_CEU20	27
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#define R8A7740_CLK_TMU0	25
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#define R8A7740_CLK_LCDC1	17
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#define R8A7740_CLK_IIC0	16
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#define R8A7740_CLK_TMU1	11
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#define R8A7740_CLK_LCDC0	0
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/* MSTP2 */
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#define R8A7740_CLK_SCIFA6	30
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#define R8A7740_CLK_INTCA	29
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#define R8A7740_CLK_SCIFA7	22
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#define R8A7740_CLK_DMAC1	18
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#define R8A7740_CLK_DMAC2	17
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#define R8A7740_CLK_DMAC3	16
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#define R8A7740_CLK_USBDMAC	14
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#define R8A7740_CLK_SCIFA5	7
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#define R8A7740_CLK_SCIFB	6
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#define R8A7740_CLK_SCIFA0	4
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#define R8A7740_CLK_SCIFA1	3
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#define R8A7740_CLK_SCIFA2	2
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#define R8A7740_CLK_SCIFA3	1
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#define R8A7740_CLK_SCIFA4	0
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/* MSTP3 */
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#define R8A7740_CLK_CMT1	29
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#define R8A7740_CLK_FSI		28
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#define R8A7740_CLK_IIC1	23
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#define R8A7740_CLK_USBF	20
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#define R8A7740_CLK_SDHI0	14
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#define R8A7740_CLK_SDHI1	13
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#define R8A7740_CLK_MMC		12
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#define R8A7740_CLK_GETHER	9
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#define R8A7740_CLK_TPU0	4
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/* MSTP4 */
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#define R8A7740_CLK_USBH	16
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#define R8A7740_CLK_SDHI2	15
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#define R8A7740_CLK_USBFUNC	7
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#define R8A7740_CLK_USBPHY	6
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/* SUBCK* */
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#define R8A7740_CLK_SUBCK	9
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#define R8A7740_CLK_SUBCK2	10
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#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */
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