8856010029
When a power domain is powered off on Exynos5420 SoC, the input clocks of the devices attached to this power domain are re-parented to oscclk and restored to the original parent after powering on the power domain. So a reference to the input and parent clocks for the devices attached to a power domain are needed to be able to do the re-parenting. The DISP1 pd includes modules which uses the following clocks: ACLK_200_DISP1 (MIXER and HDMILINK) ACLK_300_DISP1 (FIMD1) ACLK_400_DISP1 (Internal Buses) Each of these clocks are generated as the output of a clock mux so add an ID for all of these clock muxes and their parents to be referenced in the DISP1 power domain device node. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene@kernel.org>
220 lines
5.6 KiB
C
220 lines
5.6 KiB
C
/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Andrzej Hajda <a.hajda@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for Exynos5420 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
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/* core clocks */
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#define CLK_FIN_PLL 1
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#define CLK_FOUT_APLL 2
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#define CLK_FOUT_CPLL 3
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#define CLK_FOUT_DPLL 4
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#define CLK_FOUT_EPLL 5
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#define CLK_FOUT_RPLL 6
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#define CLK_FOUT_IPLL 7
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#define CLK_FOUT_SPLL 8
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#define CLK_FOUT_VPLL 9
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#define CLK_FOUT_MPLL 10
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#define CLK_FOUT_BPLL 11
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#define CLK_FOUT_KPLL 12
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/* gate for special clocks (sclk) */
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#define CLK_SCLK_UART0 128
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#define CLK_SCLK_UART1 129
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#define CLK_SCLK_UART2 130
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#define CLK_SCLK_UART3 131
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#define CLK_SCLK_MMC0 132
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#define CLK_SCLK_MMC1 133
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#define CLK_SCLK_MMC2 134
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#define CLK_SCLK_SPI0 135
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#define CLK_SCLK_SPI1 136
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#define CLK_SCLK_SPI2 137
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#define CLK_SCLK_I2S1 138
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#define CLK_SCLK_I2S2 139
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#define CLK_SCLK_PCM1 140
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#define CLK_SCLK_PCM2 141
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#define CLK_SCLK_SPDIF 142
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#define CLK_SCLK_HDMI 143
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#define CLK_SCLK_PIXEL 144
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#define CLK_SCLK_DP1 145
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#define CLK_SCLK_MIPI1 146
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#define CLK_SCLK_FIMD1 147
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#define CLK_SCLK_MAUDIO0 148
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#define CLK_SCLK_MAUPCM0 149
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#define CLK_SCLK_USBD300 150
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#define CLK_SCLK_USBD301 151
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#define CLK_SCLK_USBPHY300 152
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#define CLK_SCLK_USBPHY301 153
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#define CLK_SCLK_UNIPRO 154
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#define CLK_SCLK_PWM 155
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#define CLK_SCLK_GSCL_WA 156
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#define CLK_SCLK_GSCL_WB 157
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#define CLK_SCLK_HDMIPHY 158
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#define CLK_MAU_EPLL 159
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#define CLK_SCLK_HSIC_12M 160
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#define CLK_SCLK_MPHY_IXTAL24 161
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/* gate clocks */
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#define CLK_UART0 257
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#define CLK_UART1 258
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#define CLK_UART2 259
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#define CLK_UART3 260
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#define CLK_I2C0 261
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#define CLK_I2C1 262
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#define CLK_I2C2 263
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#define CLK_I2C3 264
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#define CLK_USI0 265
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#define CLK_USI1 266
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#define CLK_USI2 267
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#define CLK_USI3 268
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#define CLK_I2C_HDMI 269
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#define CLK_TSADC 270
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#define CLK_SPI0 271
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#define CLK_SPI1 272
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#define CLK_SPI2 273
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#define CLK_KEYIF 274
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#define CLK_I2S1 275
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#define CLK_I2S2 276
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#define CLK_PCM1 277
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#define CLK_PCM2 278
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#define CLK_PWM 279
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#define CLK_SPDIF 280
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#define CLK_USI4 281
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#define CLK_USI5 282
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#define CLK_USI6 283
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#define CLK_ACLK66_PSGEN 300
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#define CLK_CHIPID 301
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#define CLK_SYSREG 302
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#define CLK_TZPC0 303
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#define CLK_TZPC1 304
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#define CLK_TZPC2 305
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#define CLK_TZPC3 306
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#define CLK_TZPC4 307
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#define CLK_TZPC5 308
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#define CLK_TZPC6 309
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#define CLK_TZPC7 310
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#define CLK_TZPC8 311
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#define CLK_TZPC9 312
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#define CLK_HDMI_CEC 313
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#define CLK_SECKEY 314
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#define CLK_MCT 315
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#define CLK_WDT 316
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#define CLK_RTC 317
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#define CLK_TMU 318
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#define CLK_TMU_GPU 319
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#define CLK_PCLK66_GPIO 330
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#define CLK_ACLK200_FSYS2 350
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#define CLK_MMC0 351
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#define CLK_MMC1 352
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#define CLK_MMC2 353
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#define CLK_SROMC 354
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#define CLK_UFS 355
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#define CLK_ACLK200_FSYS 360
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#define CLK_TSI 361
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#define CLK_PDMA0 362
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#define CLK_PDMA1 363
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#define CLK_RTIC 364
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#define CLK_USBH20 365
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#define CLK_USBD300 366
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#define CLK_USBD301 367
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#define CLK_ACLK400_MSCL 380
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#define CLK_MSCL0 381
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#define CLK_MSCL1 382
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#define CLK_MSCL2 383
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#define CLK_SMMU_MSCL0 384
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#define CLK_SMMU_MSCL1 385
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#define CLK_SMMU_MSCL2 386
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#define CLK_ACLK333 400
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#define CLK_MFC 401
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#define CLK_SMMU_MFCL 402
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#define CLK_SMMU_MFCR 403
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#define CLK_ACLK200_DISP1 410
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#define CLK_DSIM1 411
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#define CLK_DP1 412
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#define CLK_HDMI 413
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#define CLK_ACLK300_DISP1 420
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#define CLK_FIMD1 421
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#define CLK_SMMU_FIMD1M0 422
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#define CLK_SMMU_FIMD1M1 423
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#define CLK_ACLK166 430
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#define CLK_MIXER 431
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#define CLK_ACLK266 440
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#define CLK_ROTATOR 441
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#define CLK_MDMA1 442
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#define CLK_SMMU_ROTATOR 443
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#define CLK_SMMU_MDMA1 444
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#define CLK_ACLK300_JPEG 450
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#define CLK_JPEG 451
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#define CLK_JPEG2 452
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#define CLK_SMMU_JPEG 453
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#define CLK_SMMU_JPEG2 454
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#define CLK_ACLK300_GSCL 460
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#define CLK_SMMU_GSCL0 461
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#define CLK_SMMU_GSCL1 462
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#define CLK_GSCL_WA 463
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#define CLK_GSCL_WB 464
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#define CLK_GSCL0 465
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#define CLK_GSCL1 466
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#define CLK_FIMC_3AA 467
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#define CLK_ACLK266_G2D 470
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#define CLK_SSS 471
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#define CLK_SLIM_SSS 472
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#define CLK_MDMA0 473
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#define CLK_ACLK333_G2D 480
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#define CLK_G2D 481
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#define CLK_ACLK333_432_GSCL 490
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#define CLK_SMMU_3AA 491
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#define CLK_SMMU_FIMCL0 492
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#define CLK_SMMU_FIMCL1 493
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#define CLK_SMMU_FIMCL3 494
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#define CLK_FIMC_LITE3 495
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#define CLK_FIMC_LITE0 496
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#define CLK_FIMC_LITE1 497
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#define CLK_ACLK_G3D 500
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#define CLK_G3D 501
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#define CLK_SMMU_MIXER 502
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#define CLK_SMMU_G2D 503
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#define CLK_SMMU_MDMA0 504
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#define CLK_MC 505
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#define CLK_TOP_RTC 506
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#define CLK_SCLK_UART_ISP 510
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#define CLK_SCLK_SPI0_ISP 511
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#define CLK_SCLK_SPI1_ISP 512
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#define CLK_SCLK_PWM_ISP 513
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#define CLK_SCLK_ISP_SENSOR0 514
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#define CLK_SCLK_ISP_SENSOR1 515
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#define CLK_SCLK_ISP_SENSOR2 516
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#define CLK_ACLK432_SCALER 517
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#define CLK_ACLK432_CAM 518
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#define CLK_ACLK_FL1550_CAM 519
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#define CLK_ACLK550_CAM 520
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/* mux clocks */
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#define CLK_MOUT_HDMI 640
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#define CLK_MOUT_G3D 641
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#define CLK_MOUT_VPLL 642
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#define CLK_MOUT_MAUDIO0 643
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#define CLK_MOUT_USER_ACLK333 644
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#define CLK_MOUT_SW_ACLK333 645
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#define CLK_MOUT_USER_ACLK200_DISP1 646
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#define CLK_MOUT_SW_ACLK200 647
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#define CLK_MOUT_USER_ACLK300_DISP1 648
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#define CLK_MOUT_SW_ACLK300 649
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#define CLK_MOUT_USER_ACLK400_DISP1 650
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#define CLK_MOUT_SW_ACLK400 651
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/* divider clocks */
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#define CLK_DOUT_PIXEL 768
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/* must be greater than maximal clock id */
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#define CLK_NR_CLKS 769
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
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