The users of the old method are now converted to the new one. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> [ kishon@ti.com : made phy-berlin-usb.c and phy-miphy28lp.c to use the updated devm_phy_create API.] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
		
			
				
	
	
		
			223 lines
		
	
	
	
		
			6.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			223 lines
		
	
	
	
		
			6.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright (C) 2014 Marvell Technology Group Ltd.
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 *
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 * Antoine Tenart <antoine.tenart@free-electrons.com>
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 * Jisheng Zhang <jszhang@marvell.com>
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 *
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 * This file is licensed under the terms of the GNU General Public
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 * License version 2. This program is licensed "as is" without any
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 * warranty of any kind, whether express or implied.
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 */
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#define USB_PHY_PLL		0x04
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#define USB_PHY_PLL_CONTROL	0x08
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#define USB_PHY_TX_CTRL0	0x10
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#define USB_PHY_TX_CTRL1	0x14
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#define USB_PHY_TX_CTRL2	0x18
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#define USB_PHY_RX_CTRL		0x20
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#define USB_PHY_ANALOG		0x34
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/* USB_PHY_PLL */
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#define CLK_REF_DIV(x)		((x) << 4)
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#define FEEDBACK_CLK_DIV(x)	((x) << 8)
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/* USB_PHY_PLL_CONTROL */
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#define CLK_STABLE		BIT(0)
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#define PLL_CTRL_PIN		BIT(1)
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#define PLL_CTRL_REG		BIT(2)
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#define PLL_ON			BIT(3)
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#define PHASE_OFF_TOL_125	(0x0 << 5)
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#define PHASE_OFF_TOL_250	BIT(5)
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#define KVC0_CALIB		(0x0 << 9)
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#define KVC0_REG_CTRL		BIT(9)
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#define KVC0_HIGH		(0x0 << 10)
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#define KVC0_LOW		(0x3 << 10)
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#define CLK_BLK_EN		BIT(13)
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/* USB_PHY_TX_CTRL0 */
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#define EXT_HS_RCAL_EN		BIT(3)
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#define EXT_FS_RCAL_EN		BIT(4)
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#define IMPCAL_VTH_DIV(x)	((x) << 5)
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#define EXT_RS_RCAL_DIV(x)	((x) << 8)
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#define EXT_FS_RCAL_DIV(x)	((x) << 12)
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/* USB_PHY_TX_CTRL1 */
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#define TX_VDD15_14		(0x0 << 4)
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#define TX_VDD15_15		BIT(4)
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#define TX_VDD15_16		(0x2 << 4)
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#define TX_VDD15_17		(0x3 << 4)
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#define TX_VDD12_VDD		(0x0 << 6)
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#define TX_VDD12_11		BIT(6)
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#define TX_VDD12_12		(0x2 << 6)
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#define TX_VDD12_13		(0x3 << 6)
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#define LOW_VDD_EN		BIT(8)
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#define TX_OUT_AMP(x)		((x) << 9)
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/* USB_PHY_TX_CTRL2 */
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#define TX_CHAN_CTRL_REG(x)	((x) << 0)
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#define DRV_SLEWRATE(x)		((x) << 4)
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#define IMP_CAL_FS_HS_DLY_0	(0x0 << 6)
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#define IMP_CAL_FS_HS_DLY_1	BIT(6)
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#define IMP_CAL_FS_HS_DLY_2	(0x2 << 6)
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#define IMP_CAL_FS_HS_DLY_3	(0x3 << 6)
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#define FS_DRV_EN_MASK(x)	((x) << 8)
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#define HS_DRV_EN_MASK(x)	((x) << 12)
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/* USB_PHY_RX_CTRL */
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#define PHASE_FREEZE_DLY_2_CL	(0x0 << 0)
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#define PHASE_FREEZE_DLY_4_CL	BIT(0)
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#define ACK_LENGTH_8_CL		(0x0 << 2)
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#define ACK_LENGTH_12_CL	BIT(2)
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#define ACK_LENGTH_16_CL	(0x2 << 2)
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#define ACK_LENGTH_20_CL	(0x3 << 2)
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#define SQ_LENGTH_3		(0x0 << 4)
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#define SQ_LENGTH_6		BIT(4)
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#define SQ_LENGTH_9		(0x2 << 4)
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#define SQ_LENGTH_12		(0x3 << 4)
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#define DISCON_THRESHOLD_260	(0x0 << 6)
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#define DISCON_THRESHOLD_270	BIT(6)
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#define DISCON_THRESHOLD_280	(0x2 << 6)
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#define DISCON_THRESHOLD_290	(0x3 << 6)
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#define SQ_THRESHOLD(x)		((x) << 8)
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#define LPF_COEF(x)		((x) << 12)
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#define INTPL_CUR_10		(0x0 << 14)
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#define INTPL_CUR_20		BIT(14)
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#define INTPL_CUR_30		(0x2 << 14)
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#define INTPL_CUR_40		(0x3 << 14)
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/* USB_PHY_ANALOG */
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#define ANA_PWR_UP		BIT(1)
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#define ANA_PWR_DOWN		BIT(2)
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#define V2I_VCO_RATIO(x)	((x) << 7)
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#define R_ROTATE_90		(0x0 << 10)
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#define R_ROTATE_0		BIT(10)
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#define MODE_TEST_EN		BIT(11)
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#define ANA_TEST_DC_CTRL(x)	((x) << 12)
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#define to_phy_berlin_usb_priv(p)	\
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	container_of((p), struct phy_berlin_usb_priv, phy)
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static const u32 phy_berlin_pll_dividers[] = {
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	/* Berlin 2 */
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	CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
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	/* Berlin 2CD */
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	CLK_REF_DIV(0x6) | FEEDBACK_CLK_DIV(0x55),
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};
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struct phy_berlin_usb_priv {
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	void __iomem		*base;
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	struct phy		*phy;
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	struct reset_control	*rst_ctrl;
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	u32			pll_divider;
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};
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static int phy_berlin_usb_power_on(struct phy *phy)
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{
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	struct phy_berlin_usb_priv *priv = dev_get_drvdata(phy->dev.parent);
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	reset_control_reset(priv->rst_ctrl);
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	writel(priv->pll_divider,
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	       priv->base + USB_PHY_PLL);
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	writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL |
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	       CLK_BLK_EN, priv->base + USB_PHY_PLL_CONTROL);
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	writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5),
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	       priv->base + USB_PHY_ANALOG);
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	writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 |
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	       DISCON_THRESHOLD_260 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) |
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	       INTPL_CUR_30, priv->base + USB_PHY_RX_CTRL);
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	writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1);
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	writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
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	       priv->base + USB_PHY_TX_CTRL0);
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	writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) |
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	       EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0);
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	writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
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	       priv->base + USB_PHY_TX_CTRL0);
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	writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 |
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	       FS_DRV_EN_MASK(0xd), priv->base + USB_PHY_TX_CTRL2);
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	return 0;
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}
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static struct phy_ops phy_berlin_usb_ops = {
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	.power_on	= phy_berlin_usb_power_on,
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	.owner		= THIS_MODULE,
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};
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static const struct of_device_id phy_berlin_sata_of_match[] = {
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	{
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		.compatible = "marvell,berlin2-usb-phy",
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		.data = &phy_berlin_pll_dividers[0],
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	},
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	{
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		.compatible = "marvell,berlin2cd-usb-phy",
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		.data = &phy_berlin_pll_dividers[1],
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	},
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	{ },
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};
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MODULE_DEVICE_TABLE(of, phy_berlin_sata_of_match);
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static int phy_berlin_usb_probe(struct platform_device *pdev)
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{
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	const struct of_device_id *match =
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		of_match_device(phy_berlin_sata_of_match, &pdev->dev);
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	struct phy_berlin_usb_priv *priv;
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	struct resource *res;
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	struct phy_provider *phy_provider;
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	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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	if (!priv)
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		return -ENOMEM;
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	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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	priv->base = devm_ioremap_resource(&pdev->dev, res);
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	if (IS_ERR(priv->base))
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		return PTR_ERR(priv->base);
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	priv->rst_ctrl = devm_reset_control_get(&pdev->dev, NULL);
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	if (IS_ERR(priv->rst_ctrl))
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		return PTR_ERR(priv->rst_ctrl);
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	priv->pll_divider = *((u32 *)match->data);
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	priv->phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops);
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	if (IS_ERR(priv->phy)) {
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		dev_err(&pdev->dev, "failed to create PHY\n");
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		return PTR_ERR(priv->phy);
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	}
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	platform_set_drvdata(pdev, priv);
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	phy_provider =
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		devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
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	if (IS_ERR(phy_provider))
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		return PTR_ERR(phy_provider);
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	return 0;
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}
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static struct platform_driver phy_berlin_usb_driver = {
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	.probe	= phy_berlin_usb_probe,
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	.driver	= {
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		.name		= "phy-berlin-usb",
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		.owner		= THIS_MODULE,
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		.of_match_table	= phy_berlin_sata_of_match,
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	 },
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};
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module_platform_driver(phy_berlin_usb_driver);
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MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
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MODULE_DESCRIPTION("Marvell Berlin PHY driver for USB");
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MODULE_LICENSE("GPL");
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