635c990706
Based on the spatch @@ expression e; @@ - return (e); + return e; with heavy hand editing because some of the changes are either whitespace or identation only or result in excessivly long lines. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
235 lines
6.6 KiB
C
235 lines
6.6 KiB
C
/*
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* ip22-mc.c: Routines for manipulating SGI Memory Controller.
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*
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
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* Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
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* Copyright (C) 2004 Peter Fuerst (pf@net.alphadv.de) - IP28
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <asm/sgialib.h>
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#include <asm/sgi/mc.h>
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#include <asm/sgi/hpc3.h>
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#include <asm/sgi/ip22.h>
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struct sgimc_regs *sgimc;
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EXPORT_SYMBOL(sgimc);
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static inline unsigned long get_bank_addr(unsigned int memconfig)
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{
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return (memconfig & SGIMC_MCONFIG_BASEADDR) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22);
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}
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static inline unsigned long get_bank_size(unsigned int memconfig)
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{
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return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14);
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}
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static inline unsigned int get_bank_config(int bank)
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{
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unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;
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return bank % 2 ? res & 0xffff : res >> 16;
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}
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struct mem {
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unsigned long addr;
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unsigned long size;
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};
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/*
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* Detect installed memory, do some sanity checks and notify kernel about it
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*/
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static void __init probe_memory(void)
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{
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int i, j, found, cnt = 0;
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struct mem bank[4];
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struct mem space[2] = {{SGIMC_SEG0_BADDR, 0}, {SGIMC_SEG1_BADDR, 0}};
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printk(KERN_INFO "MC: Probing memory configuration:\n");
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for (i = 0; i < ARRAY_SIZE(bank); i++) {
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unsigned int tmp = get_bank_config(i);
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if (!(tmp & SGIMC_MCONFIG_BVALID))
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continue;
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bank[cnt].size = get_bank_size(tmp);
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bank[cnt].addr = get_bank_addr(tmp);
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printk(KERN_INFO " bank%d: %3ldM @ %08lx\n",
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i, bank[cnt].size / 1024 / 1024, bank[cnt].addr);
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cnt++;
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}
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/* And you thought bubble sort is dead algorithm... */
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do {
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unsigned long addr, size;
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found = 0;
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for (i = 1; i < cnt; i++)
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if (bank[i-1].addr > bank[i].addr) {
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addr = bank[i].addr;
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size = bank[i].size;
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bank[i].addr = bank[i-1].addr;
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bank[i].size = bank[i-1].size;
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bank[i-1].addr = addr;
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bank[i-1].size = size;
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found = 1;
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}
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} while (found);
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/* Figure out how are memory banks mapped into spaces */
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for (i = 0; i < cnt; i++) {
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found = 0;
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for (j = 0; j < ARRAY_SIZE(space) && !found; j++)
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if (space[j].addr + space[j].size == bank[i].addr) {
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space[j].size += bank[i].size;
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found = 1;
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}
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/* There is either hole or overlapping memory */
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if (!found)
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printk(KERN_CRIT "MC: Memory configuration mismatch "
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"(%08lx), expect Bus Error soon\n",
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bank[i].addr);
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}
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for (i = 0; i < ARRAY_SIZE(space); i++)
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if (space[i].size)
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add_memory_region(space[i].addr, space[i].size,
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BOOT_MEM_RAM);
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}
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void __init sgimc_init(void)
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{
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u32 tmp;
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/* ioremap can't fail */
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sgimc = (struct sgimc_regs *)
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ioremap(SGIMC_BASE, sizeof(struct sgimc_regs));
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printk(KERN_INFO "MC: SGI memory controller Revision %d\n",
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(int) sgimc->systemid & SGIMC_SYSID_MASKREV);
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/* Place the MC into a known state. This must be done before
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* interrupts are first enabled etc.
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*/
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/* Step 0: Make sure we turn off the watchdog in case it's
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* still running (which might be the case after a
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* soft reboot).
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*/
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tmp = sgimc->cpuctrl0;
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tmp &= ~SGIMC_CCTRL0_WDOG;
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sgimc->cpuctrl0 = tmp;
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/* Step 1: The CPU/GIO error status registers will not latch
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* up a new error status until the register has been
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* cleared by the cpu. These status registers are
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* cleared by writing any value to them.
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*/
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sgimc->cstat = sgimc->gstat = 0;
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/* Step 2: Enable all parity checking in cpu control register
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* zero.
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*/
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/* don't touch parity settings for IP28 */
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tmp = sgimc->cpuctrl0;
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#ifndef CONFIG_SGI_IP28
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tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM;
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#endif
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tmp |= SGIMC_CCTRL0_R4KNOCHKPARR;
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sgimc->cpuctrl0 = tmp;
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/* Step 3: Setup the MC write buffer depth, this is controlled
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* in cpu control register 1 in the lower 4 bits.
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*/
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tmp = sgimc->cpuctrl1;
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tmp &= ~0xf;
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tmp |= 0xd;
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sgimc->cpuctrl1 = tmp;
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/* Step 4: Initialize the RPSS divider register to run as fast
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* as it can correctly operate. The register is laid
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* out as follows:
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*
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* ----------------------------------------
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* | RESERVED | INCREMENT | DIVIDER |
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* ----------------------------------------
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* 31 16 15 8 7 0
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*
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* DIVIDER determines how often a 'tick' happens,
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* INCREMENT determines by how the RPSS increment
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* registers value increases at each 'tick'. Thus,
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* for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
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*/
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sgimc->divider = 0x101;
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/* Step 5: Initialize GIO64 arbitrator configuration register.
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*
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* NOTE: HPC init code in sgihpc_init() must run before us because
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* we need to know Guiness vs. FullHouse and the board
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* revision on this machine. You have been warned.
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*/
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/* First the basic invariants across all GIO64 implementations. */
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tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */
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tmp |= SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */
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tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */
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if (ip22_is_fullhouse()) {
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/* Fullhouse specific settings. */
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if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
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tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */
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tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp0 pipelines */
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tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
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tmp |= SGIMC_GIOPAR_RTIMEEXP0; /* exp0 is realtime */
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} else {
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tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */
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tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */
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tmp |= SGIMC_GIOPAR_PLINEEXP1;
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tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
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}
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} else {
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/* Guiness specific settings. */
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tmp |= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */
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tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
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}
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sgimc->giopar = tmp; /* poof */
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probe_memory();
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}
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void __init prom_meminit(void) {}
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void __init prom_free_prom_memory(void)
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{
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#ifdef CONFIG_SGI_IP28
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u32 mconfig1;
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unsigned long flags;
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spinlock_t lock;
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/*
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* because ARCS accesses memory uncached we wait until ARCS
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* isn't needed any longer, before we switch from slow to
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* normal mode
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*/
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spin_lock_irqsave(&lock, flags);
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mconfig1 = sgimc->mconfig1;
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/* map ECC register */
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sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060;
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iob();
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/* switch to normal mode */
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*(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0;
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iob();
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/* reduce WR_COL */
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sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4;
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iob();
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/* restore old config */
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sgimc->mconfig1 = mconfig1;
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iob();
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spin_unlock_irqrestore(&lock, flags);
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#endif
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}
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