7352c8b13d
In CPU manual Loongson-3 is MIPS64R2 compatible, but during tests we found that its EI/DI instructions have problems. So we just set the ISA level to MIPS64R1. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/8320/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
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* Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca>
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* Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org>
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*
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* reference: /proc/cpuinfo,
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* arch/mips/kernel/cpu-probe.c(cpu_probe_legacy),
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* arch/mips/kernel/proc.c(show_cpuinfo),
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* loongson2f user manual.
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*/
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#ifndef __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H
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#define cpu_dcache_line_size() 32
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#define cpu_icache_line_size() 32
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#define cpu_scache_line_size() 32
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#define cpu_has_32fpr 1
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 1
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#define cpu_has_4kex 1
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#define cpu_has_64bits 1
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#define cpu_has_cache_cdex_p 0
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#define cpu_has_cache_cdex_s 0
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#define cpu_has_counter 1
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#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
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#define cpu_has_divec 0
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#define cpu_has_dsp 0
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#define cpu_has_dsp2 0
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#define cpu_has_ejtag 0
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#define cpu_has_fpu 1
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#define cpu_has_ic_fills_f_dc 0
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#define cpu_has_inclusive_pcaches 1
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#define cpu_has_llsc 1
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#define cpu_has_mcheck 0
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#define cpu_has_mdmx 0
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#define cpu_has_mips16 0
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#define cpu_has_mips32r2 0
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#define cpu_has_mips3d 0
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#define cpu_has_mips64r2 0
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#define cpu_has_mipsmt 0
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#define cpu_has_prefetch 0
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#define cpu_has_smartmips 0
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#define cpu_has_tlb 1
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#define cpu_has_tx39_cache 0
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#define cpu_has_userlocal 0
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#define cpu_has_vce 0
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#define cpu_has_veic 0
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#define cpu_has_vint 0
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#define cpu_has_vtag_icache 0
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#define cpu_has_watch 1
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#define cpu_has_local_ebase 0
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#define cpu_has_wsbh IS_ENABLED(CONFIG_CPU_LOONGSON3)
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#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
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