43e2be14c1
Comment incorrectly cites errata 39
E39. SDIO: SDIO Devices Not Working at 19.5 Mbps
Should be errata 38
E38. MEMC: Memory Controller hangs when entering Self Refresh Mode.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
171 lines
4.1 KiB
ArmAsm
171 lines
4.1 KiB
ArmAsm
/*
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* Low-level PXA250/210 sleep/wakeUp support
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*
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* Initial SA1110 code:
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* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
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*
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* Adapted for PXA by Nicolas Pitre:
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* Copyright (c) 2002 Monta Vista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/hardware.h>
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#include <mach/smemc.h>
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#include <mach/pxa2xx-regs.h>
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#define MDREFR_KDIV 0x200a4000 // all banks
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#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
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.text
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#ifdef CONFIG_PXA3xx
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/*
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* pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
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*/
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ENTRY(pxa3xx_finish_suspend)
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mov r0, #0x06 @ S2D3C4 mode
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mcr p14, 0, r0, c7, c0, 0 @ enter sleep
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20: b 20b @ waiting for sleep
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#endif /* CONFIG_PXA3xx */
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#ifdef CONFIG_PXA27x
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/*
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* pxa27x_finish_suspend()
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*
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* Forces CPU into sleep state.
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*
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* r0 = value for PWRMODE M field for desired sleep state
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*/
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ENTRY(pxa27x_finish_suspend)
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@ Put the processor to sleep
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@ (also workaround for sighting 28071)
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@ prepare value for sleep mode
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mov r1, r0 @ sleep mode
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@ prepare pointer to physical address 0 (virtual mapping in generic.c)
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mov r2, #UNCACHED_PHYS_0
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@ prepare SDRAM refresh settings
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ldr r4, =MDREFR
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ldr r5, [r4]
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@ enable SDRAM self-refresh mode
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orr r5, r5, #MDREFR_SLFRSH
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@ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
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ldr r6, =MDREFR_KDIV
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orr r5, r5, r6
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@ Intel PXA270 Specification Update notes problems sleeping
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@ with core operating above 91 MHz
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@ (see Errata 50, ...processor does not exit from sleep...)
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ldr r6, =CCCR
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ldr r8, [r6] @ keep original value for resume
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ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
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mov r0, #0x2 @ prepare value for CLKCFG
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@ align execution to a cache line
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b pxa_cpu_do_suspend
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#endif
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#ifdef CONFIG_PXA25x
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/*
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* pxa25x_finish_suspend()
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*
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* Forces CPU into sleep state.
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*
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* r0 = value for PWRMODE M field for desired sleep state
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*/
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ENTRY(pxa25x_finish_suspend)
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@ prepare value for sleep mode
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mov r1, r0 @ sleep mode
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@ prepare pointer to physical address 0 (virtual mapping in generic.c)
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mov r2, #UNCACHED_PHYS_0
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@ prepare SDRAM refresh settings
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ldr r4, =MDREFR
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ldr r5, [r4]
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@ enable SDRAM self-refresh mode
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orr r5, r5, #MDREFR_SLFRSH
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@ Intel PXA255 Specification Update notes problems
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@ about suspending with PXBus operating above 133MHz
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@ (see Errata 31, GPIO output signals, ... unpredictable in sleep
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@
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@ We keep the change-down close to the actual suspend on SDRAM
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@ as possible to eliminate messing about with the refresh clock
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@ as the system will restore with the original speed settings
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@
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@ Ben Dooks, 13-Sep-2004
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ldr r6, =CCCR
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ldr r8, [r6] @ keep original value for resume
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@ ensure x1 for run and turbo mode with memory clock
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bic r7, r8, #CCCR_M_MASK | CCCR_N_MASK
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orr r7, r7, #(1<<5) | (2<<7)
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@ check that the memory frequency is within limits
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and r14, r7, #CCCR_L_MASK
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teq r14, #1
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bicne r7, r7, #CCCR_L_MASK
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orrne r7, r7, #1 @@ 99.53MHz
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@ get ready for the change
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@ note, turbo is not preserved over sleep so there is no
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@ point in preserving it here. we save it on the stack with the
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@ other CP registers instead.
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mov r0, #0
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mcr p14, 0, r0, c6, c0, 0
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orr r0, r0, #2 @ initiate change bit
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b pxa_cpu_do_suspend
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#endif
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.ltorg
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.align 5
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pxa_cpu_do_suspend:
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@ All needed values are now in registers.
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@ These last instructions should be in cache
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@ initiate the frequency change...
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str r7, [r6]
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mcr p14, 0, r0, c6, c0, 0
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@ restore the original cpu speed value for resume
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str r8, [r6]
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@ need 6 13-MHz cycles before changing PWRMODE
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@ just set frequency to 91-MHz... 6*91/13 = 42
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mov r0, #42
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10: subs r0, r0, #1
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bne 10b
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@ Do not reorder...
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@ Intel PXA270 Specification Update notes problems performing
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@ external accesses after SDRAM is put in self-refresh mode
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@ (see Errata 38 ...hangs when entering self-refresh mode)
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@ force address lines low by reading at physical address 0
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ldr r3, [r2]
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@ put SDRAM into self-refresh
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str r5, [r4]
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@ enter sleep mode
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mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
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20: b 20b @ loop waiting for sleep
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