af866496c7
Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: devel@driverdev.osuosl.org Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Patchwork: https://patchwork.linux-mips.org/patch/2942/ Patchwork: https://patchwork.linux-mips.org/patch/3012/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
397 lines
12 KiB
C
397 lines
12 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/**
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*
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* This header file defines the work queue entry (wqe) data structure.
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* Since this is a commonly used structure that depends on structures
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* from several hardware blocks, those definitions have been placed
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* in this file to create a single point of definition of the wqe
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* format.
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* Data structures are still named according to the block that they
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* relate to.
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*
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*/
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#ifndef __CVMX_WQE_H__
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#define __CVMX_WQE_H__
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#include "cvmx-packet.h"
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#define OCT_TAG_TYPE_STRING(x) \
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(((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \
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(((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \
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(((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \
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"NULL_NULL")))
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/**
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* HW decode / err_code in work queue entry
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*/
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typedef union {
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uint64_t u64;
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/* Use this struct if the hardware determines that the packet is IP */
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struct {
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/* HW sets this to the number of buffers used by this packet */
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uint64_t bufs:8;
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/* HW sets to the number of L2 bytes prior to the IP */
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uint64_t ip_offset:8;
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/* set to 1 if we found DSA/VLAN in the L2 */
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uint64_t vlan_valid:1;
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/* Set to 1 if the DSA/VLAN tag is stacked */
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uint64_t vlan_stacked:1;
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uint64_t unassigned:1;
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/* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
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uint64_t vlan_cfi:1;
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/* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
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uint64_t vlan_id:12;
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/* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
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uint64_t pr:4;
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uint64_t unassigned2:8;
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/* the packet needs to be decompressed */
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uint64_t dec_ipcomp:1;
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/* the packet is either TCP or UDP */
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uint64_t tcp_or_udp:1;
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/* the packet needs to be decrypted (ESP or AH) */
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uint64_t dec_ipsec:1;
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/* the packet is IPv6 */
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uint64_t is_v6:1;
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/*
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* (rcv_error, not_IP, IP_exc, is_frag, L4_error,
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* software, etc.).
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*/
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/*
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* reserved for software use, hardware will clear on
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* packet creation.
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*/
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uint64_t software:1;
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/* exceptional conditions below */
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/* the receive interface hardware detected an L4 error
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* (only applies if !is_frag) (only applies if
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* !rcv_error && !not_IP && !IP_exc && !is_frag)
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* failure indicated in err_code below, decode:
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*
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* - 1 = Malformed L4
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* - 2 = L4 Checksum Error: the L4 checksum value is
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* - 3 = UDP Length Error: The UDP length field would
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* make the UDP data longer than what remains in
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* the IP packet (as defined by the IP header
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* length field).
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* - 4 = Bad L4 Port: either the source or destination
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* TCP/UDP port is 0.
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* - 8 = TCP FIN Only: the packet is TCP and only the
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* FIN flag set.
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* - 9 = TCP No Flags: the packet is TCP and no flags
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* are set.
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* - 10 = TCP FIN RST: the packet is TCP and both FIN
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* and RST are set.
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* - 11 = TCP SYN URG: the packet is TCP and both SYN
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* and URG are set.
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* - 12 = TCP SYN RST: the packet is TCP and both SYN
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* and RST are set.
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* - 13 = TCP SYN FIN: the packet is TCP and both SYN
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* and FIN are set.
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*/
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uint64_t L4_error:1;
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/* set if the packet is a fragment */
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uint64_t is_frag:1;
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/* the receive interface hardware detected an IP error
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* / exception (only applies if !rcv_error && !not_IP)
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* failure indicated in err_code below, decode:
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*
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* - 1 = Not IP: the IP version field is neither 4 nor
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* 6.
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* - 2 = IPv4 Header Checksum Error: the IPv4 header
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* has a checksum violation.
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* - 3 = IP Malformed Header: the packet is not long
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* enough to contain the IP header.
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* - 4 = IP Malformed: the packet is not long enough
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* to contain the bytes indicated by the IP
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* header. Pad is allowed.
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* - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
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* Hop Count field are zero.
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* - 6 = IP Options
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*/
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uint64_t IP_exc:1;
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/*
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* Set if the hardware determined that the packet is a
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* broadcast.
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*/
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uint64_t is_bcast:1;
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/*
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* St if the hardware determined that the packet is a
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* multi-cast.
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*/
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uint64_t is_mcast:1;
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/*
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* Set if the packet may not be IP (must be zero in
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* this case).
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*/
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uint64_t not_IP:1;
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/*
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* The receive interface hardware detected a receive
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* error (must be zero in this case).
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*/
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uint64_t rcv_error:1;
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/* lower err_code = first-level descriptor of the
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* work */
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/* zero for packet submitted by hardware that isn't on
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* the slow path */
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/* type is cvmx_pip_err_t */
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uint64_t err_code:8;
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} s;
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/* use this to get at the 16 vlan bits */
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struct {
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uint64_t unused1:16;
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uint64_t vlan:16;
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uint64_t unused2:32;
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} svlan;
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/*
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* use this struct if the hardware could not determine that
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* the packet is ip.
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*/
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struct {
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/*
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* HW sets this to the number of buffers used by this
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* packet.
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*/
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uint64_t bufs:8;
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uint64_t unused:8;
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/* set to 1 if we found DSA/VLAN in the L2 */
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uint64_t vlan_valid:1;
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/* Set to 1 if the DSA/VLAN tag is stacked */
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uint64_t vlan_stacked:1;
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uint64_t unassigned:1;
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/*
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* HW sets to the DSA/VLAN CFI flag (valid when
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* vlan_valid)
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*/
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uint64_t vlan_cfi:1;
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/*
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* HW sets to the DSA/VLAN_ID field (valid when
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* vlan_valid).
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*/
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uint64_t vlan_id:12;
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/*
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* Ring Identifier (if PCIe). Requires
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* PIP_GBL_CTL[RING_EN]=1
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*/
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uint64_t pr:4;
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uint64_t unassigned2:12;
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/*
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* reserved for software use, hardware will clear on
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* packet creation.
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*/
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uint64_t software:1;
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uint64_t unassigned3:1;
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/*
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* set if the hardware determined that the packet is
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* rarp.
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*/
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uint64_t is_rarp:1;
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/*
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* set if the hardware determined that the packet is
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* arp
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*/
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uint64_t is_arp:1;
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/*
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* set if the hardware determined that the packet is a
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* broadcast.
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*/
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uint64_t is_bcast:1;
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/*
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* set if the hardware determined that the packet is a
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* multi-cast
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*/
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uint64_t is_mcast:1;
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/*
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* set if the packet may not be IP (must be one in
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* this case)
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*/
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uint64_t not_IP:1;
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/* The receive interface hardware detected a receive
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* error. Failure indicated in err_code below,
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* decode:
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*
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* - 1 = partial error: a packet was partially
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* received, but internal buffering / bandwidth
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* was not adequate to receive the entire
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* packet.
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* - 2 = jabber error: the RGMII packet was too large
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* and is truncated.
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* - 3 = overrun error: the RGMII packet is longer
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* than allowed and had an FCS error.
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* - 4 = oversize error: the RGMII packet is longer
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* than allowed.
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* - 5 = alignment error: the RGMII packet is not an
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* integer number of bytes
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* and had an FCS error (100M and 10M only).
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* - 6 = fragment error: the RGMII packet is shorter
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* than allowed and had an FCS error.
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* - 7 = GMX FCS error: the RGMII packet had an FCS
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* error.
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* - 8 = undersize error: the RGMII packet is shorter
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* than allowed.
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* - 9 = extend error: the RGMII packet had an extend
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* error.
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* - 10 = length mismatch error: the RGMII packet had
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* a length that did not match the length field
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* in the L2 HDR.
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* - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
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* packet had one or more data reception errors
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* (RXERR) or the SPI4 packet had one or more
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* DIP4 errors.
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* - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
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* packet was not large enough to cover the
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* skipped bytes or the SPI4 packet was
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* terminated with an About EOPS.
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* - 13 = RGMII nibble error/SPI4 Port NXA Error: the
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* RGMII packet had a studder error (data not
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* repeated - 10/100M only) or the SPI4 packet
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* was sent to an NXA.
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* - 16 = FCS error: a SPI4.2 packet had an FCS error.
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* - 17 = Skip error: a packet was not large enough to
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* cover the skipped bytes.
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* - 18 = L2 header malformed: the packet is not long
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* enough to contain the L2.
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*/
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uint64_t rcv_error:1;
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/*
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* lower err_code = first-level descriptor of the
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* work
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*/
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/*
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* zero for packet submitted by hardware that isn't on
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* the slow path
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*/
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/* type is cvmx_pip_err_t (union, so can't use directly */
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uint64_t err_code:8;
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} snoip;
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} cvmx_pip_wqe_word2;
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/**
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* Work queue entry format
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*
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* must be 8-byte aligned
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*/
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typedef struct {
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/*****************************************************************
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* WORD 0
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* HW WRITE: the following 64 bits are filled by HW when a packet arrives
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*/
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/**
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* raw chksum result generated by the HW
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*/
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uint16_t hw_chksum;
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/**
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* Field unused by hardware - available for software
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*/
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uint8_t unused;
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/**
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* Next pointer used by hardware for list maintenance.
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* May be written/read by HW before the work queue
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* entry is scheduled to a PP
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* (Only 36 bits used in Octeon 1)
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*/
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uint64_t next_ptr:40;
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/*****************************************************************
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* WORD 1
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* HW WRITE: the following 64 bits are filled by HW when a packet arrives
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*/
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/**
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* HW sets to the total number of bytes in the packet
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*/
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uint64_t len:16;
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/**
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* HW sets this to input physical port
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*/
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uint64_t ipprt:6;
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/**
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* HW sets this to what it thought the priority of the input packet was
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*/
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uint64_t qos:3;
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/**
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* the group that the work queue entry will be scheduled to
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*/
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uint64_t grp:4;
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/**
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* the type of the tag (ORDERED, ATOMIC, NULL)
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*/
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uint64_t tag_type:3;
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/**
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* the synchronization/ordering tag
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*/
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uint64_t tag:32;
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/**
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* WORD 2 HW WRITE: the following 64-bits are filled in by
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* hardware when a packet arrives This indicates a variety of
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* status and error conditions.
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*/
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cvmx_pip_wqe_word2 word2;
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/**
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* Pointer to the first segment of the packet.
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*/
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union cvmx_buf_ptr packet_ptr;
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/**
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* HW WRITE: octeon will fill in a programmable amount from the
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* packet, up to (at most, but perhaps less) the amount
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* needed to fill the work queue entry to 128 bytes
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*
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* If the packet is recognized to be IP, the hardware starts
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* (except that the IPv4 header is padded for appropriate
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* alignment) writing here where the IP header starts. If the
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* packet is not recognized to be IP, the hardware starts
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* writing the beginning of the packet here.
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*/
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uint8_t packet_data[96];
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/**
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* If desired, SW can make the work Q entry any length. For the
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* purposes of discussion here, Assume 128B always, as this is all that
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* the hardware deals with.
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*
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*/
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} CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
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#endif /* __CVMX_WQE_H__ */
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