6741f40d19
Fix bug for DM9000 revision B which contain a DSP PHY DM9000B use DSP PHY instead previouse DM9000 revisions' analog PHY, So need extra change in initialization, For explicity PHY Reset and PHY init parameter, and first DM9000_NCR reset need NCR_MAC_LBK bit by dm9000_probe(). Following DM9000_NCR reset cause by dm9000_open() clear the NCR_MAC_LBK bit. Without this fix, Power-up FIFO pointers error happen around 2% rate among Davicom's customers' boards. With this fix, All above cases can be solved. Signed-off-by: Joseph CHANG <josright123@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
180 lines
4.9 KiB
C
180 lines
4.9 KiB
C
/*
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* dm9000 Ethernet
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*/
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#ifndef _DM9000X_H_
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#define _DM9000X_H_
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#define DM9000_ID 0x90000A46
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/* although the registers are 16 bit, they are 32-bit aligned.
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*/
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#define DM9000_NCR 0x00
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#define DM9000_NSR 0x01
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#define DM9000_TCR 0x02
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#define DM9000_TSR1 0x03
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#define DM9000_TSR2 0x04
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#define DM9000_RCR 0x05
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#define DM9000_RSR 0x06
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#define DM9000_ROCR 0x07
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#define DM9000_BPTR 0x08
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#define DM9000_FCTR 0x09
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#define DM9000_FCR 0x0A
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#define DM9000_EPCR 0x0B
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#define DM9000_EPAR 0x0C
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#define DM9000_EPDRL 0x0D
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#define DM9000_EPDRH 0x0E
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#define DM9000_WCR 0x0F
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#define DM9000_PAR 0x10
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#define DM9000_MAR 0x16
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#define DM9000_GPCR 0x1e
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#define DM9000_GPR 0x1f
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#define DM9000_TRPAL 0x22
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#define DM9000_TRPAH 0x23
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#define DM9000_RWPAL 0x24
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#define DM9000_RWPAH 0x25
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#define DM9000_VIDL 0x28
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#define DM9000_VIDH 0x29
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#define DM9000_PIDL 0x2A
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#define DM9000_PIDH 0x2B
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#define DM9000_CHIPR 0x2C
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#define DM9000_SMCR 0x2F
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#define DM9000_ETXCSR 0x30
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#define DM9000_TCCR 0x31
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#define DM9000_RCSR 0x32
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#define CHIPR_DM9000A 0x19
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#define CHIPR_DM9000B 0x1A
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#define DM9000_MRCMDX 0xF0
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#define DM9000_MRCMD 0xF2
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#define DM9000_MRRL 0xF4
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#define DM9000_MRRH 0xF5
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#define DM9000_MWCMDX 0xF6
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#define DM9000_MWCMD 0xF8
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#define DM9000_MWRL 0xFA
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#define DM9000_MWRH 0xFB
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#define DM9000_TXPLL 0xFC
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#define DM9000_TXPLH 0xFD
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#define DM9000_ISR 0xFE
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#define DM9000_IMR 0xFF
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#define NCR_EXT_PHY (1<<7)
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#define NCR_WAKEEN (1<<6)
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#define NCR_FCOL (1<<4)
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#define NCR_FDX (1<<3)
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#define NCR_RESERVED (3<<1)
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#define NCR_MAC_LBK (1<<1)
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#define NCR_RST (1<<0)
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#define NSR_SPEED (1<<7)
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#define NSR_LINKST (1<<6)
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#define NSR_WAKEST (1<<5)
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#define NSR_TX2END (1<<3)
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#define NSR_TX1END (1<<2)
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#define NSR_RXOV (1<<1)
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#define TCR_TJDIS (1<<6)
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#define TCR_EXCECM (1<<5)
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#define TCR_PAD_DIS2 (1<<4)
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#define TCR_CRC_DIS2 (1<<3)
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#define TCR_PAD_DIS1 (1<<2)
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#define TCR_CRC_DIS1 (1<<1)
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#define TCR_TXREQ (1<<0)
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#define TSR_TJTO (1<<7)
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#define TSR_LC (1<<6)
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#define TSR_NC (1<<5)
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#define TSR_LCOL (1<<4)
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#define TSR_COL (1<<3)
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#define TSR_EC (1<<2)
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#define RCR_WTDIS (1<<6)
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#define RCR_DIS_LONG (1<<5)
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#define RCR_DIS_CRC (1<<4)
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#define RCR_ALL (1<<3)
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#define RCR_RUNT (1<<2)
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#define RCR_PRMSC (1<<1)
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#define RCR_RXEN (1<<0)
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#define RSR_RF (1<<7)
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#define RSR_MF (1<<6)
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#define RSR_LCS (1<<5)
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#define RSR_RWTO (1<<4)
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#define RSR_PLE (1<<3)
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#define RSR_AE (1<<2)
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#define RSR_CE (1<<1)
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#define RSR_FOE (1<<0)
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#define WCR_LINKEN (1 << 5)
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#define WCR_SAMPLEEN (1 << 4)
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#define WCR_MAGICEN (1 << 3)
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#define WCR_LINKST (1 << 2)
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#define WCR_SAMPLEST (1 << 1)
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#define WCR_MAGICST (1 << 0)
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#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
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#define FCTR_LWOT(ot) ( ot & 0xf )
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#define IMR_PAR (1<<7)
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#define IMR_ROOM (1<<3)
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#define IMR_ROM (1<<2)
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#define IMR_PTM (1<<1)
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#define IMR_PRM (1<<0)
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#define ISR_ROOS (1<<3)
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#define ISR_ROS (1<<2)
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#define ISR_PTS (1<<1)
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#define ISR_PRS (1<<0)
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#define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
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#define EPCR_REEP (1<<5)
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#define EPCR_WEP (1<<4)
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#define EPCR_EPOS (1<<3)
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#define EPCR_ERPRR (1<<2)
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#define EPCR_ERPRW (1<<1)
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#define EPCR_ERRE (1<<0)
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#define GPCR_GEP_CNTL (1<<0)
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#define TCCR_IP (1<<0)
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#define TCCR_TCP (1<<1)
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#define TCCR_UDP (1<<2)
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#define RCSR_UDP_BAD (1<<7)
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#define RCSR_TCP_BAD (1<<6)
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#define RCSR_IP_BAD (1<<5)
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#define RCSR_UDP (1<<4)
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#define RCSR_TCP (1<<3)
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#define RCSR_IP (1<<2)
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#define RCSR_CSUM (1<<1)
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#define RCSR_DISCARD (1<<0)
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#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
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#define DM9000_PKT_ERR 0x02
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#define DM9000_PKT_MAX 1536 /* Received packet max size */
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/* DM9000A / DM9000B definitions */
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#define IMR_LNKCHNG (1<<5)
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#define IMR_UNDERRUN (1<<4)
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#define ISR_LNKCHNG (1<<5)
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#define ISR_UNDERRUN (1<<4)
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/* Davicom MII registers.
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*/
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#define MII_DM_DSPCR 0x1b /* DSP Control Register */
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#define DSPCR_INIT_PARAM 0xE100 /* DSP init parameter */
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#endif /* _DM9000X_H_ */
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