57dc7971d3
The Marvell Armada 375 SoCs contains two EHCI controllers. This commit adds the Device Tree description of these interfaces at the SoC level, and also enables the USB2 port on the Armada 375 DB platform. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1400149062-32661-18-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
137 lines
2.7 KiB
Text
137 lines
2.7 KiB
Text
/*
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* Device Tree file for Marvell Armada 375 evaluation board
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* (DB-88F6720)
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-375.dtsi"
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/ {
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model = "Marvell Armada 375 Development Board";
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compatible = "marvell,a375-db", "marvell,armada375";
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; /* 1 GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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internal-regs {
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spi@10600 {
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pinctrl-0 = <&spi0_pins>;
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pinctrl-names = "default";
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/*
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* SPI conflicts with NAND, so we disable it
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* here, and select NAND as the enabled device
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* by default.
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*/
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status = "disabled";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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};
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i2c@11000 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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};
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i2c@11100 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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};
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serial@12000 {
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status = "okay";
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};
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pinctrl {
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sdio_st_pins: sdio-st-pins {
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marvell,pins = "mpp44", "mpp45";
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marvell,function = "gpio";
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};
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};
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nand: nand@d0000 {
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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status = "okay";
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num-cs = <1>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x800000>;
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};
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partition@800000 {
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label = "Linux";
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reg = <0x800000 0x800000>;
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};
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partition@1000000 {
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label = "Filesystem";
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reg = <0x1000000 0x3f000000>;
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};
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};
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usb@54000 {
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status = "okay";
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};
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usb3@58000 {
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status = "okay";
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};
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mvsdio@d4000 {
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pinctrl-0 = <&sdio_pins &sdio_st_pins>;
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pinctrl-names = "default";
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status = "okay";
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cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* The two PCIe units are accessible through
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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