Pull MIPS updates from Ralf Baechle:
 "The most notable new addition inside this pull request is the support
  for MIPS's latest and greatest core called "inter/proAptiv".  The
  patch series describes this core as follows.
    "The interAptiv is a power-efficient multi-core microprocessor
     for use in system-on-chip (SoC) applications. The interAptiv combines
     a multi-threading pipeline with a coherence manager to deliver improved
     computational throughput and power efficiency. The interAptiv can
     contain one to four MIPS32R3 interAptiv cores, system level
     coherence manager with L2 cache, optional coherent I/O port,
     and optional floating point unit."
  The platform specific patches touch all 3 Broadcom families.  It adds
  support for the new Broadcom/Netlogix XLP9xx Soc, building a common
  BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count
  and full gpio button/led descriptions for BCM47xx.
  The rest of the series are cleanups and bug fixes that are MIPS
  generic and consist largely of changes that Imgtec/MIPS had published
  in their linux-mti-3.10.git stable tree.  Random other cleanups and
  patches preparing code to be merged in 3.15"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
  mips: select ARCH_MIGHT_HAVE_PC_SERIO
  mips: delete non-required instances of include <linux/init.h>
  MIPS: KVM: remove shadow_tlb code
  MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI
  mips/ide: flush dcache also if icache does not snoop dcache
  MIPS: BCM47XX: fix position of cpu_wait disabling
  MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
  MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>
  MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>
  MIPS: ZBOOT: gather string functions into string.c
  arch/mips/pci: don't check resource with devm_ioremap_resource
  arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource
  bcma: gpio: don't cast u32 to unsigned long
  ssb: gpio: add own IRQ domain
  MIPS: BCM47XX: fix sparse warnings in board.c
  MIPS: BCM47XX: add board detection for Linksys WRT54GS V1
  MIPS: BCM47XX: fix detection for some boards
  MIPS: BCM47XX: Enable buttons support on SSB
  MIPS: BCM47XX: Convert WNDR4500 to new syntax
  MIPS: BCM47XX: Use "timer" trigger for status LEDs
  ...
		
	
			
		
			
				
	
	
		
			210 lines
		
	
	
	
		
			5.5 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			210 lines
		
	
	
	
		
			5.5 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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 * reserved.
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 *
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 * This software is available to you under a choice of one of two
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 * licenses.  You may choose to be licensed under the terms of the GNU
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 * General Public License (GPL) Version 2, available from the file
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 * COPYING in the main directory of this source tree, or the NetLogic
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 * license below:
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in
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 *    the documentation and/or other materials provided with the
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 *    distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include <linux/kernel.h>
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#include <linux/serial_8250.h>
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#include <linux/pm.h>
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#include <asm/idle.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/bootinfo.h>
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#include <asm/netlogic/interrupt.h>
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#include <asm/netlogic/psb-bootinfo.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/xlr/xlr.h>
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#include <asm/netlogic/xlr/iomap.h>
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#include <asm/netlogic/xlr/pic.h>
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#include <asm/netlogic/xlr/gpio.h>
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#include <asm/netlogic/xlr/fmn.h>
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uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE;
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struct psb_info nlm_prom_info;
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/* default to uniprocessor */
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unsigned int  nlm_threads_per_core = 1;
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struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
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cpumask_t nlm_cpumask = CPU_MASK_CPU0;
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static void nlm_linux_exit(void)
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{
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	uint64_t gpiobase;
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	gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
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	/* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
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	nlm_write_reg(gpiobase, GPIO_SWRESET_REG, 1);
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	for ( ; ; )
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		cpu_wait();
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}
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void __init plat_mem_setup(void)
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{
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	_machine_restart = (void (*)(char *))nlm_linux_exit;
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	_machine_halt	= nlm_linux_exit;
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	pm_power_off	= nlm_linux_exit;
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}
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const char *get_system_type(void)
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{
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	return "Netlogic XLR/XLS Series";
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}
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unsigned int nlm_get_cpu_frequency(void)
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{
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	return (unsigned int)nlm_prom_info.cpu_frequency;
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}
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void __init prom_free_prom_memory(void)
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{
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	/* Nothing yet */
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}
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void nlm_percpu_init(int hwcpuid)
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{
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	if (hwcpuid % 4 == 0)
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		xlr_percpu_fmn_init();
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}
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static void __init build_arcs_cmdline(int *argv)
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{
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	int i, remain, len;
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	char *arg;
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	remain = sizeof(arcs_cmdline) - 1;
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	arcs_cmdline[0] = '\0';
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	for (i = 0; argv[i] != 0; i++) {
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		arg = (char *)(long)argv[i];
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		len = strlen(arg);
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		if (len + 1 > remain)
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			break;
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		strcat(arcs_cmdline, arg);
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		strcat(arcs_cmdline, " ");
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		remain -=  len + 1;
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	}
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	/* Add the default options here */
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	if ((strstr(arcs_cmdline, "console=")) == NULL) {
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		arg = "console=ttyS0,38400 ";
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		len = strlen(arg);
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		if (len > remain)
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			goto fail;
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		strcat(arcs_cmdline, arg);
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		remain -= len;
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	}
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#ifdef CONFIG_BLK_DEV_INITRD
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	if ((strstr(arcs_cmdline, "rdinit=")) == NULL) {
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		arg = "rdinit=/sbin/init ";
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		len = strlen(arg);
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		if (len > remain)
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			goto fail;
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		strcat(arcs_cmdline, arg);
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		remain -= len;
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	}
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#endif
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	return;
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fail:
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	panic("Cannot add %s, command line too big!", arg);
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}
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static void prom_add_memory(void)
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{
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	struct nlm_boot_mem_map *bootm;
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	u64 start, size;
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	u64 pref_backup = 512;	/* avoid pref walking beyond end */
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	int i;
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	bootm = (void *)(long)nlm_prom_info.psb_mem_map;
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	for (i = 0; i < bootm->nr_map; i++) {
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		if (bootm->map[i].type != BOOT_MEM_RAM)
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			continue;
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		start = bootm->map[i].addr;
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		size   = bootm->map[i].size;
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		/* Work around for using bootloader mem */
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		if (i == 0 && start == 0 && size == 0x0c000000)
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			size = 0x0ff00000;
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		add_memory_region(start, size - pref_backup, BOOT_MEM_RAM);
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	}
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}
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static void nlm_init_node(void)
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{
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	struct nlm_soc_info *nodep;
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	nodep = nlm_current_node();
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	nodep->picbase = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
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	nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
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	spin_lock_init(&nodep->piclock);
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}
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void __init prom_init(void)
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{
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	int *argv, *envp;		/* passed as 32 bit ptrs */
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	struct psb_info *prom_infop;
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	void *reset_vec;
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#ifdef CONFIG_SMP
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	int i;
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#endif
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	/* truncate to 32 bit and sign extend all args */
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	argv = (int *)(long)(int)fw_arg1;
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	envp = (int *)(long)(int)fw_arg2;
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	prom_infop = (struct psb_info *)(long)(int)fw_arg3;
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	nlm_prom_info = *prom_infop;
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	nlm_init_node();
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	/* Update reset entry point with CPU init code */
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	reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS);
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	memset(reset_vec, 0, RESET_VEC_SIZE);
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	memcpy(reset_vec, (void *)nlm_reset_entry,
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			(nlm_reset_entry_end - nlm_reset_entry));
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	build_arcs_cmdline(argv);
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	prom_add_memory();
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#ifdef CONFIG_SMP
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	for (i = 0; i < 32; i++)
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		if (nlm_prom_info.online_cpu_map & (1 << i))
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			cpumask_set_cpu(i, &nlm_cpumask);
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	nlm_wakeup_secondary_cpus();
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	register_smp_ops(&nlm_smp_ops);
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#endif
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	xlr_board_info_setup();
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	xlr_percpu_fmn_init();
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}
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