705314797b
The shadow register 0x1C is used both by the BCM54xxx PHYs and the BCM7xxx internal PHYs, move the accessors to a common location so both drivers can use them. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
687 lines
17 KiB
C
687 lines
17 KiB
C
/*
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* drivers/net/phy/broadcom.c
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*
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* Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
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* transceivers.
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*
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* Copyright (c) 2006 Maciej W. Rozycki
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*
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* Inspired by code written by Amy Fong.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/brcmphy.h>
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#define BRCM_PHY_MODEL(phydev) \
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((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
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#define BRCM_PHY_REV(phydev) \
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((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
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MODULE_DESCRIPTION("Broadcom PHY driver");
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MODULE_AUTHOR("Maciej W. Rozycki");
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MODULE_LICENSE("GPL");
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/* Indirect register access functions for the Expansion Registers */
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static int bcm54xx_exp_read(struct phy_device *phydev, u16 regnum)
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{
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int val;
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val = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
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if (val < 0)
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return val;
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val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
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/* Restore default value. It's O.K. if this write fails. */
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phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
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return val;
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}
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static int bcm54xx_exp_write(struct phy_device *phydev, u16 regnum, u16 val)
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{
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int ret;
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ret = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
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if (ret < 0)
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return ret;
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ret = phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
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/* Restore default value. It's O.K. if this write fails. */
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phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
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return ret;
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}
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static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
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{
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return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
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}
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/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
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static int bcm50610_a0_workaround(struct phy_device *phydev)
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{
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int err;
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err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH0,
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MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
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MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
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if (err < 0)
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return err;
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err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH3,
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MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
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if (err < 0)
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return err;
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err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75,
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MII_BCM54XX_EXP_EXP75_VDACCTRL);
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if (err < 0)
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return err;
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err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP96,
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MII_BCM54XX_EXP_EXP96_MYST);
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if (err < 0)
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return err;
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err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP97,
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MII_BCM54XX_EXP_EXP97_MYST);
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return err;
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}
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static int bcm54xx_phydsp_config(struct phy_device *phydev)
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{
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int err, err2;
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/* Enable the SMDSP clock */
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err = bcm54xx_auxctl_write(phydev,
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MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
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MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
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MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
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if (err < 0)
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return err;
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if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
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/* Clear bit 9 to fix a phy interop issue. */
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err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP08,
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MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
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if (err < 0)
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goto error;
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if (phydev->drv->phy_id == PHY_ID_BCM50610) {
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err = bcm50610_a0_workaround(phydev);
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if (err < 0)
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goto error;
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}
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}
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if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
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int val;
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val = bcm54xx_exp_read(phydev, MII_BCM54XX_EXP_EXP75);
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if (val < 0)
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goto error;
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val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
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err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75, val);
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}
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error:
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/* Disable the SMDSP clock */
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err2 = bcm54xx_auxctl_write(phydev,
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MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
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MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
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/* Return the first error reported. */
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return err ? err : err2;
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}
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static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
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{
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u32 orig;
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int val;
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bool clk125en = true;
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/* Abort if we are using an untested phy. */
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if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
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return;
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val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
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if (val < 0)
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return;
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orig = val;
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if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
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BRCM_PHY_REV(phydev) >= 0x3) {
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/*
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* Here, bit 0 _disables_ CLK125 when set.
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* This bit is set by default.
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*/
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clk125en = false;
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} else {
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if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
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/* Here, bit 0 _enables_ CLK125 when set */
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val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
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clk125en = false;
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}
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}
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if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
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val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
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else
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val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
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if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
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val |= BCM54XX_SHD_SCR3_TRDDAPD;
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if (orig != val)
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bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
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val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
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if (val < 0)
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return;
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orig = val;
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if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
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val |= BCM54XX_SHD_APD_EN;
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else
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val &= ~BCM54XX_SHD_APD_EN;
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if (orig != val)
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bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
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}
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static int bcm54xx_config_init(struct phy_device *phydev)
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{
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int reg, err;
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reg = phy_read(phydev, MII_BCM54XX_ECR);
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if (reg < 0)
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return reg;
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/* Mask interrupts globally. */
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reg |= MII_BCM54XX_ECR_IM;
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err = phy_write(phydev, MII_BCM54XX_ECR, reg);
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if (err < 0)
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return err;
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/* Unmask events we are interested in. */
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reg = ~(MII_BCM54XX_INT_DUPLEX |
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MII_BCM54XX_INT_SPEED |
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MII_BCM54XX_INT_LINK);
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err = phy_write(phydev, MII_BCM54XX_IMR, reg);
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if (err < 0)
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return err;
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if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
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(phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
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bcm54xx_shadow_write(phydev, BCM54XX_SHD_RGMII_MODE, 0);
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if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
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(phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
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(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
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bcm54xx_adjust_rxrefclk(phydev);
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bcm54xx_phydsp_config(phydev);
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return 0;
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}
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static int bcm5482_config_init(struct phy_device *phydev)
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{
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int err, reg;
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err = bcm54xx_config_init(phydev);
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if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
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/*
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* Enable secondary SerDes and its use as an LED source
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*/
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reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_SSD);
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bcm54xx_shadow_write(phydev, BCM5482_SHD_SSD,
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reg |
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BCM5482_SHD_SSD_LEDM |
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BCM5482_SHD_SSD_EN);
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/*
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* Enable SGMII slave mode and auto-detection
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*/
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reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
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err = bcm54xx_exp_read(phydev, reg);
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if (err < 0)
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return err;
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err = bcm54xx_exp_write(phydev, reg, err |
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BCM5482_SSD_SGMII_SLAVE_EN |
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BCM5482_SSD_SGMII_SLAVE_AD);
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if (err < 0)
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return err;
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/*
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* Disable secondary SerDes powerdown
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*/
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reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
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err = bcm54xx_exp_read(phydev, reg);
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if (err < 0)
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return err;
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err = bcm54xx_exp_write(phydev, reg,
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err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
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if (err < 0)
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return err;
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/*
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* Select 1000BASE-X register set (primary SerDes)
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*/
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reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_MODE);
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bcm54xx_shadow_write(phydev, BCM5482_SHD_MODE,
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reg | BCM5482_SHD_MODE_1000BX);
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/*
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* LED1=ACTIVITYLED, LED3=LINKSPD[2]
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* (Use LED1 as secondary SerDes ACTIVITY LED)
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*/
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bcm54xx_shadow_write(phydev, BCM5482_SHD_LEDS1,
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BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
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BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
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/*
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* Auto-negotiation doesn't seem to work quite right
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* in this mode, so we disable it and force it to the
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* right speed/duplex setting. Only 'link status'
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* is important.
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*/
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phydev->autoneg = AUTONEG_DISABLE;
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phydev->speed = SPEED_1000;
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phydev->duplex = DUPLEX_FULL;
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}
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return err;
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}
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static int bcm5482_read_status(struct phy_device *phydev)
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{
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int err;
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err = genphy_read_status(phydev);
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if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
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/*
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* Only link status matters for 1000Base-X mode, so force
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* 1000 Mbit/s full-duplex status
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*/
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if (phydev->link) {
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phydev->speed = SPEED_1000;
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phydev->duplex = DUPLEX_FULL;
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}
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}
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return err;
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}
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static int bcm54xx_ack_interrupt(struct phy_device *phydev)
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{
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int reg;
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/* Clear pending interrupts. */
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reg = phy_read(phydev, MII_BCM54XX_ISR);
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if (reg < 0)
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return reg;
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return 0;
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}
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static int bcm54xx_config_intr(struct phy_device *phydev)
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{
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int reg, err;
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reg = phy_read(phydev, MII_BCM54XX_ECR);
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if (reg < 0)
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return reg;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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reg &= ~MII_BCM54XX_ECR_IM;
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else
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reg |= MII_BCM54XX_ECR_IM;
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err = phy_write(phydev, MII_BCM54XX_ECR, reg);
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return err;
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}
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static int bcm5481_config_aneg(struct phy_device *phydev)
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{
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int ret;
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/* Aneg firsly. */
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ret = genphy_config_aneg(phydev);
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/* Then we can set up the delay. */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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u16 reg;
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/*
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* There is no BCM5481 specification available, so down
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* here is everything we know about "register 0x18". This
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* at least helps BCM5481 to successfully receive packets
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* on MPC8360E-RDK board. Peter Barada <peterb@logicpd.com>
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* says: "This sets delay between the RXD and RXC signals
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* instead of using trace lengths to achieve timing".
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*/
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/* Set RDX clk delay. */
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reg = 0x7 | (0x7 << 12);
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phy_write(phydev, 0x18, reg);
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reg = phy_read(phydev, 0x18);
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/* Set RDX-RXC skew. */
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reg |= (1 << 8);
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/* Write bits 14:0. */
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reg |= (1 << 15);
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phy_write(phydev, 0x18, reg);
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}
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return ret;
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}
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static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
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{
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int val;
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val = phy_read(phydev, reg);
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if (val < 0)
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return val;
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return phy_write(phydev, reg, val | set);
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}
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static int brcm_fet_config_init(struct phy_device *phydev)
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{
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int reg, err, err2, brcmtest;
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/* Reset the PHY to bring it to a known state. */
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err = phy_write(phydev, MII_BMCR, BMCR_RESET);
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if (err < 0)
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return err;
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reg = phy_read(phydev, MII_BRCM_FET_INTREG);
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if (reg < 0)
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return reg;
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/* Unmask events we are interested in and mask interrupts globally. */
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reg = MII_BRCM_FET_IR_DUPLEX_EN |
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MII_BRCM_FET_IR_SPEED_EN |
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MII_BRCM_FET_IR_LINK_EN |
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MII_BRCM_FET_IR_ENABLE |
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MII_BRCM_FET_IR_MASK;
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err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
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if (err < 0)
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return err;
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/* Enable shadow register access */
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brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
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if (brcmtest < 0)
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return brcmtest;
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reg = brcmtest | MII_BRCM_FET_BT_SRE;
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err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
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if (err < 0)
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return err;
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/* Set the LED mode */
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reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
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if (reg < 0) {
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err = reg;
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goto done;
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}
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reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
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reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
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err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
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if (err < 0)
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goto done;
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/* Enable auto MDIX */
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err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
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MII_BRCM_FET_SHDW_MC_FAME);
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if (err < 0)
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goto done;
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if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
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/* Enable auto power down */
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err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
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MII_BRCM_FET_SHDW_AS2_APDE);
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}
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done:
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/* Disable shadow register access */
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err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
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if (!err)
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err = err2;
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return err;
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}
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static int brcm_fet_ack_interrupt(struct phy_device *phydev)
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{
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int reg;
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/* Clear pending interrupts. */
|
|
reg = phy_read(phydev, MII_BRCM_FET_INTREG);
|
|
if (reg < 0)
|
|
return reg;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int brcm_fet_config_intr(struct phy_device *phydev)
|
|
{
|
|
int reg, err;
|
|
|
|
reg = phy_read(phydev, MII_BRCM_FET_INTREG);
|
|
if (reg < 0)
|
|
return reg;
|
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
|
reg &= ~MII_BRCM_FET_IR_MASK;
|
|
else
|
|
reg |= MII_BRCM_FET_IR_MASK;
|
|
|
|
err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
|
|
return err;
|
|
}
|
|
|
|
static struct phy_driver broadcom_drivers[] = {
|
|
{
|
|
.phy_id = PHY_ID_BCM5411,
|
|
.phy_id_mask = 0xfffffff0,
|
|
.name = "Broadcom BCM5411",
|
|
.features = PHY_GBIT_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = bcm54xx_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = bcm54xx_ack_interrupt,
|
|
.config_intr = bcm54xx_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
}, {
|
|
.phy_id = PHY_ID_BCM5421,
|
|
.phy_id_mask = 0xfffffff0,
|
|
.name = "Broadcom BCM5421",
|
|
.features = PHY_GBIT_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = bcm54xx_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = bcm54xx_ack_interrupt,
|
|
.config_intr = bcm54xx_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
}, {
|
|
.phy_id = PHY_ID_BCM5461,
|
|
.phy_id_mask = 0xfffffff0,
|
|
.name = "Broadcom BCM5461",
|
|
.features = PHY_GBIT_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = bcm54xx_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = bcm54xx_ack_interrupt,
|
|
.config_intr = bcm54xx_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
}, {
|
|
.phy_id = PHY_ID_BCM5464,
|
|
.phy_id_mask = 0xfffffff0,
|
|
.name = "Broadcom BCM5464",
|
|
.features = PHY_GBIT_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = bcm54xx_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = bcm54xx_ack_interrupt,
|
|
.config_intr = bcm54xx_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
}, {
|
|
.phy_id = PHY_ID_BCM5481,
|
|
.phy_id_mask = 0xfffffff0,
|
|
.name = "Broadcom BCM5481",
|
|
.features = PHY_GBIT_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = bcm54xx_config_init,
|
|
.config_aneg = bcm5481_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = bcm54xx_ack_interrupt,
|
|
.config_intr = bcm54xx_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
}, {
|
|
.phy_id = PHY_ID_BCM5482,
|
|
.phy_id_mask = 0xfffffff0,
|
|
.name = "Broadcom BCM5482",
|
|
.features = PHY_GBIT_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = bcm5482_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = bcm5482_read_status,
|
|
.ack_interrupt = bcm54xx_ack_interrupt,
|
|
.config_intr = bcm54xx_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
}, {
|
|
.phy_id = PHY_ID_BCM50610,
|
|
.phy_id_mask = 0xfffffff0,
|
|
.name = "Broadcom BCM50610",
|
|
.features = PHY_GBIT_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = bcm54xx_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = bcm54xx_ack_interrupt,
|
|
.config_intr = bcm54xx_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
}, {
|
|
.phy_id = PHY_ID_BCM50610M,
|
|
.phy_id_mask = 0xfffffff0,
|
|
.name = "Broadcom BCM50610M",
|
|
.features = PHY_GBIT_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = bcm54xx_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = bcm54xx_ack_interrupt,
|
|
.config_intr = bcm54xx_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
}, {
|
|
.phy_id = PHY_ID_BCM57780,
|
|
.phy_id_mask = 0xfffffff0,
|
|
.name = "Broadcom BCM57780",
|
|
.features = PHY_GBIT_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = bcm54xx_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = bcm54xx_ack_interrupt,
|
|
.config_intr = bcm54xx_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
}, {
|
|
.phy_id = PHY_ID_BCMAC131,
|
|
.phy_id_mask = 0xfffffff0,
|
|
.name = "Broadcom BCMAC131",
|
|
.features = PHY_BASIC_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = brcm_fet_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = brcm_fet_ack_interrupt,
|
|
.config_intr = brcm_fet_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
}, {
|
|
.phy_id = PHY_ID_BCM5241,
|
|
.phy_id_mask = 0xfffffff0,
|
|
.name = "Broadcom BCM5241",
|
|
.features = PHY_BASIC_FEATURES |
|
|
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = brcm_fet_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = brcm_fet_ack_interrupt,
|
|
.config_intr = brcm_fet_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
} };
|
|
|
|
static int __init broadcom_init(void)
|
|
{
|
|
return phy_drivers_register(broadcom_drivers,
|
|
ARRAY_SIZE(broadcom_drivers));
|
|
}
|
|
|
|
static void __exit broadcom_exit(void)
|
|
{
|
|
phy_drivers_unregister(broadcom_drivers,
|
|
ARRAY_SIZE(broadcom_drivers));
|
|
}
|
|
|
|
module_init(broadcom_init);
|
|
module_exit(broadcom_exit);
|
|
|
|
static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
|
|
{ PHY_ID_BCM5411, 0xfffffff0 },
|
|
{ PHY_ID_BCM5421, 0xfffffff0 },
|
|
{ PHY_ID_BCM5461, 0xfffffff0 },
|
|
{ PHY_ID_BCM5464, 0xfffffff0 },
|
|
{ PHY_ID_BCM5482, 0xfffffff0 },
|
|
{ PHY_ID_BCM5482, 0xfffffff0 },
|
|
{ PHY_ID_BCM50610, 0xfffffff0 },
|
|
{ PHY_ID_BCM50610M, 0xfffffff0 },
|
|
{ PHY_ID_BCM57780, 0xfffffff0 },
|
|
{ PHY_ID_BCMAC131, 0xfffffff0 },
|
|
{ PHY_ID_BCM5241, 0xfffffff0 },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, broadcom_tbl);
|