7546d2f48d
Loongson family machines has three types of serial port: PCI UART, LPC UART and CPU internal UART. Loongson-2E and parts of Loongson-2F based machines use PCI UART; most Loongson-2F based machines use LPC UART; Loongson-2G/3A has both LPC and CPU UART but usually use CPU UART. Port address of UARTs: CPU UART: REG_BASE + OFFSET; LPC UART: LIO1_BASE + OFFSET; PCI UART: PCIIO_BASE + OFFSET. Since LPC UART are linked in "Local Bus", both CPU UART and LPC UART are called "CPU provided serial port". Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6635 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
80 lines
2.3 KiB
C
80 lines
2.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
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*
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* Copyright (C) 2009 Lemote, Inc.
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* Author: Yan hua (yanhua@lemote.com)
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* Author: Wu Zhangjin (wuzhangjin@gmail.com)
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*/
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/serial_8250.h>
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#include <asm/bootinfo.h>
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#include <loongson.h>
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#include <machine.h>
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#define PORT(int, clk) \
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{ \
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.irq = int, \
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.uartclk = clk, \
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.iotype = UPIO_PORT, \
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
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.regshift = 0, \
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}
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#define PORT_M(int, clk) \
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{ \
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.irq = MIPS_CPU_IRQ_BASE + (int), \
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.uartclk = clk, \
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.iotype = UPIO_MEM, \
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.membase = (void __iomem *)NULL, \
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
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.regshift = 0, \
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}
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static struct plat_serial8250_port uart8250_data[][2] = {
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[MACH_LOONGSON_UNKNOWN] {},
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[MACH_LEMOTE_FL2E] {PORT(4, 1843200), {} },
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[MACH_LEMOTE_FL2F] {PORT(3, 1843200), {} },
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[MACH_LEMOTE_ML2F7] {PORT_M(3, 3686400), {} },
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[MACH_LEMOTE_YL2F89] {PORT_M(3, 3686400), {} },
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[MACH_DEXXON_GDIUM2F10] {PORT_M(3, 3686400), {} },
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[MACH_LEMOTE_NAS] {PORT_M(3, 3686400), {} },
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[MACH_LEMOTE_LL2F] {PORT(3, 1843200), {} },
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[MACH_LEMOTE_A1004] {PORT_M(2, 33177600), {} },
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[MACH_LEMOTE_A1101] {PORT_M(2, 25000000), {} },
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[MACH_LEMOTE_A1201] {PORT_M(2, 25000000), {} },
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[MACH_LEMOTE_A1205] {PORT_M(2, 25000000), {} },
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[MACH_LOONGSON_END] {},
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};
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static struct platform_device uart8250_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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};
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static int __init serial_init(void)
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{
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unsigned char iotype;
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iotype = uart8250_data[mips_machtype][0].iotype;
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if (UPIO_MEM == iotype)
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uart8250_data[mips_machtype][0].membase =
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(void __iomem *)_loongson_uart_base;
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else if (UPIO_PORT == iotype)
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uart8250_data[mips_machtype][0].iobase =
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loongson_uart_base - LOONGSON_PCIIO_BASE;
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uart8250_device.dev.platform_data = uart8250_data[mips_machtype];
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return platform_device_register(&uart8250_device);
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}
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device_initcall(serial_init);
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