7034228792
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
149 lines
3.9 KiB
C
149 lines
3.9 KiB
C
/*
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* the OHCI Virtual Support Module of AMD CS5536
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*
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* Copyright (C) 2007 Lemote, Inc.
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* Author : jlliu, liujl@lemote.com
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*
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* Copyright (C) 2009 Lemote, Inc.
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* Author: Wu Zhangjin, wuzhangjin@gmail.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <cs5536/cs5536.h>
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#include <cs5536/cs5536_pci.h>
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void pci_ohci_write_reg(int reg, u32 value)
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{
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u32 hi = 0, lo = value;
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switch (reg) {
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case PCI_COMMAND:
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_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
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if (value & PCI_COMMAND_MASTER)
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hi |= PCI_COMMAND_MASTER;
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else
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hi &= ~PCI_COMMAND_MASTER;
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if (value & PCI_COMMAND_MEMORY)
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hi |= PCI_COMMAND_MEMORY;
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else
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hi &= ~PCI_COMMAND_MEMORY;
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_wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
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break;
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case PCI_STATUS:
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if (value & PCI_STATUS_PARITY) {
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_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
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if (lo & SB_PARE_ERR_FLAG) {
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lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
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_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
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}
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}
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break;
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case PCI_BAR0_REG:
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if (value == PCI_BAR_RANGE_MASK) {
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_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
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lo |= SOFT_BAR_OHCI_FLAG;
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_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
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} else if ((value & 0x01) == 0x00) {
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_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
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lo = value;
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_wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
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value &= 0xfffffff0;
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hi = 0x40000000 | ((value & 0xff000000) >> 24);
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lo = 0x000fffff | ((value & 0x00fff000) << 8);
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_wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
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}
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break;
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case PCI_OHCI_INT_REG:
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_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
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lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
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if (value) /* enable all the usb interrupt in PIC */
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lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
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_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
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break;
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default:
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break;
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}
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}
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u32 pci_ohci_read_reg(int reg)
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{
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u32 conf_data = 0;
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u32 hi, lo;
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switch (reg) {
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case PCI_VENDOR_ID:
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conf_data =
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CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
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break;
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case PCI_COMMAND:
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_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
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if (hi & PCI_COMMAND_MASTER)
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conf_data |= PCI_COMMAND_MASTER;
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if (hi & PCI_COMMAND_MEMORY)
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conf_data |= PCI_COMMAND_MEMORY;
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break;
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case PCI_STATUS:
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conf_data |= PCI_STATUS_66MHZ;
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conf_data |= PCI_STATUS_FAST_BACK;
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_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
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if (lo & SB_PARE_ERR_FLAG)
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conf_data |= PCI_STATUS_PARITY;
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conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
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break;
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case PCI_CLASS_REVISION:
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_rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
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conf_data = lo & 0x000000ff;
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conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
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break;
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case PCI_CACHE_LINE_SIZE:
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conf_data =
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CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
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PCI_NORMAL_LATENCY_TIMER);
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break;
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case PCI_BAR0_REG:
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_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
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if (lo & SOFT_BAR_OHCI_FLAG) {
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conf_data = CS5536_OHCI_RANGE |
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PCI_BASE_ADDRESS_SPACE_MEMORY;
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lo &= ~SOFT_BAR_OHCI_FLAG;
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_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
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} else {
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_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
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conf_data = lo & 0xffffff00;
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conf_data &= ~0x0000000f; /* 32bit mem */
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}
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break;
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case PCI_CARDBUS_CIS:
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conf_data = PCI_CARDBUS_CIS_POINTER;
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break;
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case PCI_SUBSYSTEM_VENDOR_ID:
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conf_data =
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CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
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break;
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case PCI_ROM_ADDRESS:
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conf_data = PCI_EXPANSION_ROM_BAR;
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break;
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case PCI_CAPABILITY_LIST:
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conf_data = PCI_CAPLIST_USB_POINTER;
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break;
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case PCI_INTERRUPT_LINE:
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conf_data =
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CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
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break;
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case PCI_OHCI_INT_REG:
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_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
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if ((lo & 0x00000f00) == CS5536_USB_INTR)
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conf_data = 1;
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break;
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default:
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break;
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}
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return conf_data;
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}
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