ded1e9d727
The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
108 lines
3.5 KiB
C
108 lines
3.5 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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*/
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#ifndef _MT7620_REGS_H_
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#define _MT7620_REGS_H_
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#define MT7620_SYSC_BASE 0x10000000
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#define SYSC_REG_CHIP_NAME0 0x00
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#define SYSC_REG_CHIP_NAME1 0x04
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#define SYSC_REG_CHIP_REV 0x0c
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#define SYSC_REG_SYSTEM_CONFIG0 0x10
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#define SYSC_REG_SYSTEM_CONFIG1 0x14
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#define SYSC_REG_CLKCFG0 0x2c
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#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
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#define SYSC_REG_CPLL_CONFIG0 0x54
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#define SYSC_REG_CPLL_CONFIG1 0x58
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#define MT7620N_CHIP_NAME0 0x33365452
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#define MT7620N_CHIP_NAME1 0x20203235
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#define MT7620A_CHIP_NAME0 0x3637544d
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#define MT7620A_CHIP_NAME1 0x20203032
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#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
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#define CHIP_REV_PKG_MASK 0x1
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#define CHIP_REV_PKG_SHIFT 16
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#define CHIP_REV_VER_MASK 0xf
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#define CHIP_REV_VER_SHIFT 8
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#define CHIP_REV_ECO_MASK 0xf
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#define CLKCFG0_PERI_CLK_SEL BIT(4)
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#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
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#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
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#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
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#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
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#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
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#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
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#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
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#define CPLL_CFG0_SW_CFG BIT(31)
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#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
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#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
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#define CPLL_CFG0_LC_CURFCK BIT(15)
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#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
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#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
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#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
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#define CPLL_CFG1_CPU_AUX1 BIT(25)
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#define CPLL_CFG1_CPU_AUX0 BIT(24)
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#define SYSCFG0_DRAM_TYPE_MASK 0x3
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#define SYSCFG0_DRAM_TYPE_SHIFT 4
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#define SYSCFG0_DRAM_TYPE_SDRAM 0
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#define SYSCFG0_DRAM_TYPE_DDR1 1
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#define SYSCFG0_DRAM_TYPE_DDR2 2
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#define MT7620_DRAM_BASE 0x0
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#define MT7620_SDRAM_SIZE_MIN 2
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#define MT7620_SDRAM_SIZE_MAX 64
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#define MT7620_DDR1_SIZE_MIN 32
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#define MT7620_DDR1_SIZE_MAX 128
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#define MT7620_DDR2_SIZE_MIN 32
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#define MT7620_DDR2_SIZE_MAX 256
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#define MT7620_GPIO_MODE_I2C BIT(0)
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#define MT7620_GPIO_MODE_UART0_SHIFT 2
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#define MT7620_GPIO_MODE_UART0_MASK 0x7
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#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
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#define MT7620_GPIO_MODE_UARTF 0x0
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#define MT7620_GPIO_MODE_PCM_UARTF 0x1
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#define MT7620_GPIO_MODE_PCM_I2S 0x2
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#define MT7620_GPIO_MODE_I2S_UARTF 0x3
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#define MT7620_GPIO_MODE_PCM_GPIO 0x4
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#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
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#define MT7620_GPIO_MODE_GPIO_I2S 0x6
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#define MT7620_GPIO_MODE_GPIO 0x7
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#define MT7620_GPIO_MODE_UART1 BIT(5)
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#define MT7620_GPIO_MODE_MDIO BIT(8)
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#define MT7620_GPIO_MODE_RGMII1 BIT(9)
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#define MT7620_GPIO_MODE_RGMII2 BIT(10)
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#define MT7620_GPIO_MODE_SPI BIT(11)
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#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
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#define MT7620_GPIO_MODE_WLED BIT(13)
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#define MT7620_GPIO_MODE_JTAG BIT(15)
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#define MT7620_GPIO_MODE_EPHY BIT(15)
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#define MT7620_GPIO_MODE_WDT BIT(22)
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#endif
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