0f3a05cb43
Now that Yosemite's gone we can move the MSP71xx code one level up. Shane McDonald <mcdonald.shane@gmail.com>'s https://patchwork.linux-mips.org/patch/4736/ has been folded into this patch. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
664 lines
26 KiB
C
664 lines
26 KiB
C
/*
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* Defines for the address space, registers and register configuration
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* (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
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* This file contains addess maps for all the devices in the line of
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* products but only has register definitions and configuration masks for
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* registers which aren't definitely associated with any device. Things
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* like clock settings, reset access, the ELB etc. Individual device
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* drivers will reference the appropriate XXX_BASE value defined here
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* and have individual registers offset from that.
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*
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* Copyright (C) 2005-2007 PMC-Sierra, Inc. All rights reserved.
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* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*/
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#include <asm/addrspace.h>
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#include <linux/types.h>
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#ifndef _ASM_MSP_REGS_H
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#define _ASM_MSP_REGS_H
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/*
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########################################################################
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# Address space and device base definitions #
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########################################################################
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*/
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/*
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***************************************************************************
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* System Logic and Peripherals (ELB, UART0, etc) device address space *
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***************************************************************************
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*/
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#define MSP_SLP_BASE 0x1c000000
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/* System Logic and Peripherals */
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#define MSP_RST_BASE (MSP_SLP_BASE + 0x10)
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/* System reset register base */
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#define MSP_RST_SIZE 0x0C /* System reset register space */
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#define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C)
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/* watchdog timer base */
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#define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054)
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/* internal timer base */
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#define MSP_UART0_BASE (MSP_SLP_BASE + 0x100)
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/* UART0 controller base */
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#define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120)
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/* Block Copy controller base */
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#define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160)
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/* Block Copy descriptor base */
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/*
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***************************************************************************
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* PCI address space *
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***************************************************************************
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*/
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#define MSP_PCI_BASE 0x19000000
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/*
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***************************************************************************
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* MSbus device address space *
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***************************************************************************
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*/
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#define MSP_MSB_BASE 0x18000000
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/* MSbus address start */
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#define MSP_PER_BASE (MSP_MSB_BASE + 0x400000)
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/* Peripheral device registers */
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#define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000)
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/* MAC A device registers */
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#define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000)
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/* MAC B device registers */
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#define MSP_MAC_SIZE 0xE0 /* MAC register space */
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#define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000)
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/* Security Engine registers */
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#define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000)
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/* MAC C device registers */
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#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000)
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/* ADSL2 device registers */
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#define MSP_USB0_BASE (MSP_MSB_BASE + 0xB00000)
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/* USB0 device registers */
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#define MSP_USB1_BASE (MSP_MSB_BASE + 0x300000)
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/* USB1 device registers */
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#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000)
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/* CPU interface registers */
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/* Devices within the MSbus peripheral block */
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#define MSP_UART1_BASE (MSP_PER_BASE + 0x030)
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/* UART1 controller base */
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#define MSP_SPI_BASE (MSP_PER_BASE + 0x058)
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/* SPI/MPI control registers */
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#define MSP_TWI_BASE (MSP_PER_BASE + 0x090)
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/* Two-wire control registers */
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#define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0)
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/* Programmable timer control */
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/*
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***************************************************************************
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* Physical Memory configuration address space *
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***************************************************************************
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*/
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#define MSP_MEM_CFG_BASE 0x17f00000
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#define MSP_MEM_INDIRECT_CTL_10 0x10
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/*
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* Notes:
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* 1) The SPI registers are split into two blocks, one offset from the
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* MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
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* 0x68. The SPI driver definitions for the register must be aware
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* of this.
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* 2) The block copy engine register are divided into two regions, one
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* for the control/configuration of the engine proper and one for the
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* values of the descriptors used in the copy process. These have
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* different base defines (CTRL_BASE vs DESC_BASE)
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* 3) These constants are for physical addresses which means that they
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* work correctly with "ioremap" and friends. This means that device
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* drivers will need to remap these addresses using ioremap and perhaps
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* the readw/writew macros. Or they could use the regptr() macro
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* defined below, but the readw/writew calls are the correct thing.
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* 4) The UARTs have an additional status register offset from the base
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* address. This register isn't used in the standard 8250 driver but
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* may be used in other software. Consult the hardware datasheet for
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* offset details.
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* 5) For some unknown reason the security engine (MSP_SEC_BASE) registers
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* start at an offset of 0x84 from the base address but the block of
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* registers before this is reserved for the security engine. The
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* driver will have to be aware of this but it makes the register
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* definitions line up better with the documentation.
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*/
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/*
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########################################################################
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# System register definitions. Not associated with a specific device #
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########################################################################
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*/
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/*
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* This macro maps the physical register number into uncached space
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* and (for C code) casts it into a u32 pointer so it can be dereferenced
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* Normally these would be accessed with ioremap and readX/writeX, but
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* these are convenient for a lot of internal kernel code.
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*/
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#ifdef __ASSEMBLER__
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#define regptr(addr) (KSEG1ADDR(addr))
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#else
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#define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
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#endif
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/*
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***************************************************************************
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* System Logic and Peripherals (RESET, ELB, etc) registers *
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***************************************************************************
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*/
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/* System Control register definitions */
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#define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00)
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/* Device-ID RO */
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#define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04)
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/* Firmware-ID Register RW */
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#define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08)
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/* System-ID Register-0 RW */
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#define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C)
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/* System-ID Register-1 RW */
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/* System Reset register definitions */
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#define RST_STS_REG regptr(MSP_SLP_BASE + 0x10)
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/* System Reset Status RO */
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#define RST_SET_REG regptr(MSP_SLP_BASE + 0x14)
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/* System Set Reset WO */
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#define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18)
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/* System Clear Reset WO */
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/* System Clock Registers */
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#define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C)
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/* PCI clock generator RW */
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#define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20)
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/* UART clock generator RW */
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/* reserved (MSP_SLP_BASE + 0x24) */
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/* reserved (MSP_SLP_BASE + 0x28) */
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#define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C)
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/* PLL1 clock generator RW */
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#define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30)
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/* PLL0 clock generator RW */
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#define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34)
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/* MIPS clock generator RW */
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#define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38)
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/* Voice Eng clock generator RW */
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/* reserved (MSP_SLP_BASE + 0x3C) */
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#define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40)
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/* MS-Bus clock generator RW */
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#define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44)
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/* Sec & MAC clock generator RW */
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#define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48)
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/* Per & TDM clock generator RW */
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/* Interrupt Controller Registers */
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#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
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/* Interrupt status register RW */
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#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
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/* Interrupt enable/mask RW */
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#define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78)
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/* Security Engine mailbox RW */
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#define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C)
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/* Voice Engine mailbox RW */
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/* ELB Controller Registers */
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#define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80)
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/* ELB CS0 Configuration Reg */
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#define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84)
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/* ELB CS0 Base Address Reg */
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#define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88)
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/* ELB CS0 Mask Register */
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#define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)
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/* ELB CS0 access register */
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#define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90)
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/* ELB CS1 Configuration Reg */
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#define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94)
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/* ELB CS1 Base Address Reg */
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#define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98)
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/* ELB CS1 Mask Register */
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#define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)
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/* ELB CS1 access register */
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#define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0)
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/* ELB CS2 Configuration Reg */
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#define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4)
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/* ELB CS2 Base Address Reg */
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#define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8)
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/* ELB CS2 Mask Register */
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#define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)
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/* ELB CS2 access register */
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#define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0)
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/* ELB CS3 Configuration Reg */
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#define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4)
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/* ELB CS3 Base Address Reg */
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#define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8)
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/* ELB CS3 Mask Register */
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#define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)
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/* ELB CS3 access register */
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#define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0)
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/* ELB CS4 Configuration Reg */
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#define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4)
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/* ELB CS4 Base Address Reg */
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#define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8)
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/* ELB CS4 Mask Register */
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#define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)
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/* ELB CS4 access register */
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#define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0)
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/* ELB CS5 Configuration Reg */
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#define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4)
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/* ELB CS5 Base Address Reg */
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#define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8)
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/* ELB CS5 Mask Register */
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#define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)
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/* ELB CS5 access register */
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/* reserved 0xE0 - 0xE8 */
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#define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)
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/* ELB single PC card detect */
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/* reserved 0xF0 - 0xF8 */
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#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
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/* SDRAM read/ELB timing Reg */
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/* Extended UART status registers */
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#define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0)
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/* UART Status Register 0 */
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#define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170)
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/* UART Status Register 1 */
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/* Performance monitoring registers */
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#define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140)
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/* Performance monitor control */
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#define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144)
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/* Performance monitor clear */
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#define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148)
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/* Perf monitor counter high */
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#define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C)
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/* Perf monitor counter low */
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/* System control registers */
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#define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150)
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/* System control register */
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#define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154)
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/* System Error status 1 */
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#define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158)
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/* System Error status 2 */
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#define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C)
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/* System Interrupt config */
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/* Voice Engine Memory configuration */
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#define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C)
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/* Voice engine memory config */
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/* CPU/SLP Error Status registers */
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#define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180)
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/* CPU/SLP Error status 1 */
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#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)
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/* CPU/SLP Error status 1 */
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/* Extended GPIO registers */
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#define EXTENDED_GPIO1_REG regptr(MSP_SLP_BASE + 0x188)
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#define EXTENDED_GPIO2_REG regptr(MSP_SLP_BASE + 0x18c)
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#define EXTENDED_GPIO_REG EXTENDED_GPIO1_REG
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/* Backward-compatibility */
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/* System Error registers */
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#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)
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/* Int status for SLP errors */
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#define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194)
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/* Int mask for SLP errors */
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#define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198)
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/* External ELB reset */
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#define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C)
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/* Boot Status */
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/* Extended ELB addressing */
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#define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0)
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/* CS0 Extended address */
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#define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4)
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/* CS1 Extended address */
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#define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8)
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/* CS2 Extended address */
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#define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC)
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/* CS3 Extended address */
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/* reserved 0x1B0 */
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#define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4)
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/* CS5 Extended address */
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/* PLL Adjustment registers */
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#define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200)
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/* PLL0 lock status */
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#define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204)
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/* PLL Analog reset status */
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#define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208)
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/* PLL0 Adjustment value */
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#define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C)
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/* PLL1 Adjustment value */
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/*
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***************************************************************************
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* Peripheral Register definitions *
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***************************************************************************
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*/
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/* Peripheral status */
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#define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50)
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/* Peripheral control register */
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#define PER_STS_REG regptr(MSP_PER_BASE + 0x54)
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/* Peripheral status register */
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/* SPI/MPI Registers */
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#define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58)
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/* SPI/MPI Tx Size register */
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#define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C)
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/* SPI/MPI Rx Size register */
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#define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60)
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/* SPI/MPI Control register */
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#define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64)
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/* SPI/MPI Chip Select reg */
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#define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0)
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/* SPI/MPI Core Data reg */
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#define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4)
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/* SPI/MPI Core Control reg */
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#define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8)
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/* SPI/MPI Core Status reg */
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#define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC)
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/* SPI/MPI Core Ssel reg */
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#define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0)
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/* SPI/MPI Data FIFO reg */
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/* Peripheral Block Error Registers */
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#define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70)
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/* Error Bit Status Register */
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#define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74)
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/* Error Bit Mask Register */
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#define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78)
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/* Error Header 1 Register */
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#define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C)
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/* Error Header 2 Register */
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/* Peripheral Block Interrupt Registers */
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#define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80)
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/* Interrupt status register */
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#define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84)
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/* Interrupt Mask Register */
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#define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88)
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/* GPIO interrupt status reg */
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#define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C)
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/* GPIO interrupt MASK Reg */
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/* POLO GPIO registers */
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#define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0)
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/* Polo GPIO[8:0] data reg */
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#define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4)
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/* Polo GPIO[7:0] config reg */
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#define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8)
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/* Polo GPIO[15:8] config reg */
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#define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC)
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/* Polo GPIO[31:0] output drive */
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#define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170)
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/* Polo GPIO[23:16] config reg */
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#define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174)
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/* Polo GPIO[15:9] data reg */
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#define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178)
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/* Polo GPIO[23:16] data reg */
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#define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C)
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/* Polo GPIO[31:24] data reg */
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#define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180)
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/* Polo GPIO[39:32] data reg */
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#define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184)
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/* Polo GPIO[47:40] data reg */
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#define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188)
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/* Polo GPIO[54:48] data reg */
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#define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
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/* Polo GPIO[31:24] config reg */
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#define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190)
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/* Polo GPIO[39:32] config reg */
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#define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194)
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/* Polo GPIO[47:40] config reg */
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#define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198)
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/* Polo GPIO[54:48] config reg */
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#define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C)
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/* Polo GPIO[54:32] output drive */
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/* Generic GPIO registers */
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#define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170)
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/* GPIO[1:0] data register */
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#define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174)
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/* GPIO[5:2] data register */
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#define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178)
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/* GPIO[9:6] data register */
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#define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C)
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/* GPIO[15:10] data register */
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#define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180)
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/* GPIO[1:0] config register */
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#define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184)
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/* GPIO[5:2] config register */
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#define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188)
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/* GPIO[9:6] config register */
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#define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
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/* GPIO[15:10] config register */
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#define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190)
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/* GPIO[15:0] output drive */
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/*
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***************************************************************************
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* CPU Interface register definitions *
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|
***************************************************************************
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*/
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#define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00)
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/* PCI-SDRAM queue flush trigger */
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#define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04)
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/* OCP Error Attribute 1 */
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#define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08)
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/* OCP Error Attribute 2 */
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#define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C)
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/* OCP Error Status */
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#define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10)
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/* CPU policy configuration */
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#define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10)
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/* Misc configuration options */
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/* Central Interrupt Controller Registers */
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#define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000)
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/* Central Interrupt registers */
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#define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00)
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/* External interrupt config */
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|
#define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04)
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/* CIC Interrupt Status */
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#define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08)
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/* VPE0 Interrupt Mask */
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#define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C)
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/* VPE1 Interrupt Mask */
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#define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10)
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|
/* Thread Context 0 Int Mask */
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|
#define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14)
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|
/* Thread Context 1 Int Mask */
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|
#define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18)
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|
/* Thread Context 2 Int Mask */
|
|
#define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18)
|
|
/* Thread Context 3 Int Mask */
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|
#define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18)
|
|
/* Thread Context 4 Int Mask */
|
|
#define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18)
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|
#define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18)
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|
#define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18)
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#define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08)
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|
|
|
|
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/*
|
|
***************************************************************************
|
|
* Memory controller registers *
|
|
***************************************************************************
|
|
*/
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|
#define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00)
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|
#define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00)
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#define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04)
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|
#define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08)
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|
|
|
/*
|
|
***************************************************************************
|
|
* PCI controller registers *
|
|
***************************************************************************
|
|
*/
|
|
#define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00)
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|
#define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800)
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|
#define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c)
|
|
|
|
/*
|
|
########################################################################
|
|
# Register content & macro definitions #
|
|
########################################################################
|
|
*/
|
|
|
|
/*
|
|
***************************************************************************
|
|
* DEV_ID defines *
|
|
***************************************************************************
|
|
*/
|
|
#define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */
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|
#define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */
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|
#define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */
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|
#define DEV_ID_FAMILY (0xff << 8) /* family ID code */
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|
#define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */
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|
|
|
#define MSPFPGA_ID (0x00 << 8) /* you are on your own here */
|
|
#define MSP5000_ID (0x50 << 8)
|
|
#define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */
|
|
#define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */
|
|
#define MSP4200_ID (0x42 << 8)
|
|
#define MSP4000_ID (0x40 << 8)
|
|
#define MSP2XXX_ID (0x20 << 8)
|
|
#define MSPZEUS_ID (0x10 << 8)
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|
|
|
#define MSP2004_SUB_ID (0x0 << 16)
|
|
#define MSP2005_SUB_ID (0x1 << 16)
|
|
#define MSP2006_SUB_ID (0x1 << 16)
|
|
#define MSP2007_SUB_ID (0x2 << 16)
|
|
#define MSP2010_SUB_ID (0x3 << 16)
|
|
#define MSP2015_SUB_ID (0x4 << 16)
|
|
#define MSP2020_SUB_ID (0x5 << 16)
|
|
#define MSP2100_SUB_ID (0x6 << 16)
|
|
|
|
/*
|
|
***************************************************************************
|
|
* RESET defines *
|
|
***************************************************************************
|
|
*/
|
|
#define MSP_GR_RST (0x01 << 0) /* Global reset bit */
|
|
#define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */
|
|
#define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */
|
|
#define MSP_PP_RST (0x01 << 3) /* PVC reset bit */
|
|
/* reserved */
|
|
#define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */
|
|
#define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */
|
|
#define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */
|
|
#define MSP_PB_RST (0x01 << 9) /* Per block reset bit */
|
|
#define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */
|
|
#define MSP_TW_RST (0x01 << 11) /* TWI reset bit */
|
|
#define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */
|
|
#define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */
|
|
#define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */
|
|
|
|
/*
|
|
***************************************************************************
|
|
* UART defines *
|
|
***************************************************************************
|
|
*/
|
|
#define MSP_BASE_BAUD 25000000
|
|
#define MSP_UART_REG_LEN 0x20
|
|
|
|
/*
|
|
***************************************************************************
|
|
* ELB defines *
|
|
***************************************************************************
|
|
*/
|
|
#define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */
|
|
#define SINGLE_PCCARD 0x01 /* Set to enable single PC card */
|
|
|
|
/*
|
|
***************************************************************************
|
|
* CIC defines *
|
|
***************************************************************************
|
|
*/
|
|
|
|
/* CIC_EXT_CFG_REG */
|
|
#define EXT_INT_POL(eirq) (1 << (eirq + 8))
|
|
#define EXT_INT_EDGE(eirq) (1 << eirq)
|
|
|
|
#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq))
|
|
#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq))
|
|
#define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq))
|
|
#define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq))
|
|
#define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI
|
|
#define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO
|
|
|
|
#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
|
|
((reg & EXT_INT_EDGE(eirq)) == 0)
|
|
#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq))
|
|
#define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq))
|
|
#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
|
|
((reg & EXT_INT_POL(eirq)) == 0)
|
|
#define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI
|
|
#define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO
|
|
|
|
/*
|
|
***************************************************************************
|
|
* Memory Controller defines *
|
|
***************************************************************************
|
|
*/
|
|
|
|
/* Indirect memory controller registers */
|
|
#define DDRC_CFG(n) (n)
|
|
#define DDRC_DEBUG(n) (0x04 + n)
|
|
#define DDRC_CTL(n) (0x40 + n)
|
|
|
|
/* Macro to perform DDRC indirect write */
|
|
#define DDRC_INDIRECT_WRITE(reg, mask, value) \
|
|
({ \
|
|
*MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
|
|
*MEM_SS_DATA = (value); \
|
|
*MEM_SS_WRITE = 1; \
|
|
})
|
|
|
|
/*
|
|
***************************************************************************
|
|
* SPI/MPI Mode *
|
|
***************************************************************************
|
|
*/
|
|
#define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */
|
|
#define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */
|
|
#define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */
|
|
#define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */
|
|
|
|
/*
|
|
***************************************************************************
|
|
* SPI/MPI Control Register *
|
|
***************************************************************************
|
|
*/
|
|
#define SPI_MPI_RX_START 0x00000004 /* Start receive command */
|
|
#define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */
|
|
#define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */
|
|
|
|
#endif /* !_ASM_MSP_REGS_H */
|