5d472b7377
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Signed-off-by: David S. Miller <davem@davemloft.net>
183 lines
6.6 KiB
C
183 lines
6.6 KiB
C
/*
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Written 1994 by David C. Davies.
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Copyright 1994 David C. Davies. This software may be used and distributed
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according to the terms of the GNU General Public License, incorporated herein by
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reference.
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*/
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/*
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** I/O addresses. Note that the 2k buffer option is not supported in
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** this driver.
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*/
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#define DEPCA_NICSR ioaddr+0x00 /* Network interface CSR */
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#define DEPCA_RBI ioaddr+0x02 /* RAM buffer index (2k buffer mode) */
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#define DEPCA_DATA ioaddr+0x04 /* LANCE registers' data port */
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#define DEPCA_ADDR ioaddr+0x06 /* LANCE registers' address port */
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#define DEPCA_HBASE ioaddr+0x08 /* EISA high memory base address reg. */
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#define DEPCA_PROM ioaddr+0x0c /* Ethernet address ROM data port */
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#define DEPCA_CNFG ioaddr+0x0c /* EISA Configuration port */
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#define DEPCA_RBSA ioaddr+0x0e /* RAM buffer starting address (2k buff.) */
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/*
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** These are LANCE registers addressable through DEPCA_ADDR
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*/
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#define CSR0 0
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#define CSR1 1
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#define CSR2 2
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#define CSR3 3
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/*
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** NETWORK INTERFACE CSR (NI_CSR) bit definitions
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*/
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#define TO 0x0100 /* Time Out for remote boot */
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#define SHE 0x0080 /* SHadow memory Enable */
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#define BS 0x0040 /* Bank Select */
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#define BUF 0x0020 /* BUFfer size (1->32k, 0->64k) */
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#define RBE 0x0010 /* Remote Boot Enable (1->net boot) */
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#define AAC 0x0008 /* Address ROM Address Counter (1->enable) */
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#define _128KB 0x0008 /* 128kB Network RAM (1->enable) */
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#define IM 0x0004 /* Interrupt Mask (1->mask) */
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#define IEN 0x0002 /* Interrupt tristate ENable (1->enable) */
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#define LED 0x0001 /* LED control */
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/*
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** Control and Status Register 0 (CSR0) bit definitions
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*/
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#define ERR 0x8000 /* Error summary */
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#define BABL 0x4000 /* Babble transmitter timeout error */
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#define CERR 0x2000 /* Collision Error */
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#define MISS 0x1000 /* Missed packet */
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#define MERR 0x0800 /* Memory Error */
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#define RINT 0x0400 /* Receiver Interrupt */
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#define TINT 0x0200 /* Transmit Interrupt */
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#define IDON 0x0100 /* Initialization Done */
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#define INTR 0x0080 /* Interrupt Flag */
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#define INEA 0x0040 /* Interrupt Enable */
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#define RXON 0x0020 /* Receiver on */
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#define TXON 0x0010 /* Transmitter on */
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#define TDMD 0x0008 /* Transmit Demand */
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#define STOP 0x0004 /* Stop */
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#define STRT 0x0002 /* Start */
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#define INIT 0x0001 /* Initialize */
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#define INTM 0xff00 /* Interrupt Mask */
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#define INTE 0xfff0 /* Interrupt Enable */
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/*
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** CONTROL AND STATUS REGISTER 3 (CSR3)
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*/
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#define BSWP 0x0004 /* Byte SWaP */
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#define ACON 0x0002 /* ALE control */
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#define BCON 0x0001 /* Byte CONtrol */
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/*
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** Initialization Block Mode Register
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*/
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#define PROM 0x8000 /* Promiscuous Mode */
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#define EMBA 0x0080 /* Enable Modified Back-off Algorithm */
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#define INTL 0x0040 /* Internal Loopback */
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#define DRTY 0x0020 /* Disable Retry */
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#define COLL 0x0010 /* Force Collision */
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#define DTCR 0x0008 /* Disable Transmit CRC */
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#define LOOP 0x0004 /* Loopback */
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#define DTX 0x0002 /* Disable the Transmitter */
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#define DRX 0x0001 /* Disable the Receiver */
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/*
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** Receive Message Descriptor 1 (RMD1) bit definitions.
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*/
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#define R_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
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#define R_ERR 0x4000 /* Error Summary */
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#define R_FRAM 0x2000 /* Framing Error */
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#define R_OFLO 0x1000 /* Overflow Error */
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#define R_CRC 0x0800 /* CRC Error */
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#define R_BUFF 0x0400 /* Buffer Error */
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#define R_STP 0x0200 /* Start of Packet */
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#define R_ENP 0x0100 /* End of Packet */
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/*
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** Transmit Message Descriptor 1 (TMD1) bit definitions.
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*/
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#define T_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
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#define T_ERR 0x4000 /* Error Summary */
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#define T_ADD_FCS 0x2000 /* More the 1 retry needed to Xmit */
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#define T_MORE 0x1000 /* >1 retry to transmit packet */
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#define T_ONE 0x0800 /* 1 try needed to transmit the packet */
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#define T_DEF 0x0400 /* Deferred */
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#define T_STP 0x02000000 /* Start of Packet */
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#define T_ENP 0x01000000 /* End of Packet */
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#define T_FLAGS 0xff000000 /* TX Flags Field */
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/*
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** Transmit Message Descriptor 3 (TMD3) bit definitions.
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*/
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#define TMD3_BUFF 0x8000 /* BUFFer error */
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#define TMD3_UFLO 0x4000 /* UnderFLOw error */
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#define TMD3_RES 0x2000 /* REServed */
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#define TMD3_LCOL 0x1000 /* Late COLlision */
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#define TMD3_LCAR 0x0800 /* Loss of CARrier */
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#define TMD3_RTRY 0x0400 /* ReTRY error */
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/*
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** EISA configuration Register (CNFG) bit definitions
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*/
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#define TIMEOUT 0x0100 /* 0:2.5 mins, 1: 30 secs */
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#define REMOTE 0x0080 /* Remote Boot Enable -> 1 */
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#define IRQ11 0x0040 /* Enable -> 1 */
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#define IRQ10 0x0020 /* Enable -> 1 */
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#define IRQ9 0x0010 /* Enable -> 1 */
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#define IRQ5 0x0008 /* Enable -> 1 */
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#define BUFF 0x0004 /* 0: 64kB or 128kB, 1: 32kB */
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#define PADR16 0x0002 /* RAM on 64kB boundary */
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#define PADR17 0x0001 /* RAM on 128kB boundary */
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/*
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** Miscellaneous
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*/
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#define HASH_TABLE_LEN 64 /* Bits */
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#define HASH_BITS 0x003f /* 6 LS bits */
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#define MASK_INTERRUPTS 1
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#define UNMASK_INTERRUPTS 0
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#define EISA_EN 0x0001 /* Enable EISA bus buffers */
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#define EISA_ID iobase+0x0080 /* ID long word for EISA card */
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#define EISA_CTRL iobase+0x0084 /* Control word for EISA card */
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/*
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** Include the IOCTL stuff
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*/
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#include <linux/sockios.h>
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struct depca_ioctl {
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unsigned short cmd; /* Command to run */
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unsigned short len; /* Length of the data buffer */
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unsigned char __user *data; /* Pointer to the data buffer */
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};
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/*
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** Recognised commands for the driver
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*/
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#define DEPCA_GET_HWADDR 0x01 /* Get the hardware address */
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#define DEPCA_SET_HWADDR 0x02 /* Get the hardware address */
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#define DEPCA_SET_PROM 0x03 /* Set Promiscuous Mode */
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#define DEPCA_CLR_PROM 0x04 /* Clear Promiscuous Mode */
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#define DEPCA_SAY_BOO 0x05 /* Say "Boo!" to the kernel log file */
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#define DEPCA_GET_MCA 0x06 /* Get a multicast address */
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#define DEPCA_SET_MCA 0x07 /* Set a multicast address */
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#define DEPCA_CLR_MCA 0x08 /* Clear a multicast address */
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#define DEPCA_MCA_EN 0x09 /* Enable a multicast address group */
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#define DEPCA_GET_STATS 0x0a /* Get the driver statistics */
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#define DEPCA_CLR_STATS 0x0b /* Zero out the driver statistics */
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#define DEPCA_GET_REG 0x0c /* Get the Register contents */
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#define DEPCA_SET_REG 0x0d /* Set the Register contents */
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#define DEPCA_DUMP 0x0f /* Dump the DEPCA Status */
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