Wolfram Sang pointed out that "efm32,$device" is non-standard. So use the common scheme and prefix device with "efm32-". The old compatible string is left in place until arch/arm/boot/dts/efm32* is fixed. Acked-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
		
			
				
	
	
		
			276 lines
		
	
	
	
		
			6.5 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			276 lines
		
	
	
	
		
			6.5 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright (C) 2013 Pengutronix
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 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
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 *
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 * This program is free software; you can redistribute it and/or modify it under
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 * the terms of the GNU General Public License version 2 as published by the
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 * Free Software Foundation.
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 */
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#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/clk.h>
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#define TIMERn_CTRL			0x00
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#define TIMERn_CTRL_PRESC(val)			(((val) & 0xf) << 24)
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#define TIMERn_CTRL_PRESC_1024			TIMERn_CTRL_PRESC(10)
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#define TIMERn_CTRL_CLKSEL(val)			(((val) & 0x3) << 16)
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#define TIMERn_CTRL_CLKSEL_PRESCHFPERCLK	TIMERn_CTRL_CLKSEL(0)
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#define TIMERn_CTRL_OSMEN			0x00000010
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#define TIMERn_CTRL_MODE(val)			(((val) & 0x3) <<  0)
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#define TIMERn_CTRL_MODE_UP			TIMERn_CTRL_MODE(0)
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#define TIMERn_CTRL_MODE_DOWN			TIMERn_CTRL_MODE(1)
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#define TIMERn_CMD			0x04
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#define TIMERn_CMD_START			0x00000001
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#define TIMERn_CMD_STOP				0x00000002
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#define TIMERn_IEN			0x0c
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#define TIMERn_IF			0x10
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#define TIMERn_IFS			0x14
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#define TIMERn_IFC			0x18
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#define TIMERn_IRQ_UF				0x00000002
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#define TIMERn_TOP			0x1c
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#define TIMERn_CNT			0x24
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struct efm32_clock_event_ddata {
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	struct clock_event_device evtdev;
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	void __iomem *base;
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	unsigned periodic_top;
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};
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static void efm32_clock_event_set_mode(enum clock_event_mode mode,
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				       struct clock_event_device *evtdev)
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{
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	struct efm32_clock_event_ddata *ddata =
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		container_of(evtdev, struct efm32_clock_event_ddata, evtdev);
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	switch (mode) {
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	case CLOCK_EVT_MODE_PERIODIC:
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		writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD);
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		writel_relaxed(ddata->periodic_top, ddata->base + TIMERn_TOP);
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		writel_relaxed(TIMERn_CTRL_PRESC_1024 |
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			       TIMERn_CTRL_CLKSEL_PRESCHFPERCLK |
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			       TIMERn_CTRL_MODE_DOWN,
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			       ddata->base + TIMERn_CTRL);
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		writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD);
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		break;
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	case CLOCK_EVT_MODE_ONESHOT:
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		writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD);
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		writel_relaxed(TIMERn_CTRL_PRESC_1024 |
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			       TIMERn_CTRL_CLKSEL_PRESCHFPERCLK |
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			       TIMERn_CTRL_OSMEN |
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			       TIMERn_CTRL_MODE_DOWN,
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			       ddata->base + TIMERn_CTRL);
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		break;
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	case CLOCK_EVT_MODE_UNUSED:
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	case CLOCK_EVT_MODE_SHUTDOWN:
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		writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD);
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		break;
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	case CLOCK_EVT_MODE_RESUME:
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		break;
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	}
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}
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static int efm32_clock_event_set_next_event(unsigned long evt,
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					    struct clock_event_device *evtdev)
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{
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	struct efm32_clock_event_ddata *ddata =
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		container_of(evtdev, struct efm32_clock_event_ddata, evtdev);
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	writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD);
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	writel_relaxed(evt, ddata->base + TIMERn_CNT);
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	writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD);
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	return 0;
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}
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static irqreturn_t efm32_clock_event_handler(int irq, void *dev_id)
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{
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	struct efm32_clock_event_ddata *ddata = dev_id;
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	writel_relaxed(TIMERn_IRQ_UF, ddata->base + TIMERn_IFC);
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	ddata->evtdev.event_handler(&ddata->evtdev);
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	return IRQ_HANDLED;
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}
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static struct efm32_clock_event_ddata clock_event_ddata = {
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	.evtdev = {
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		.name = "efm32 clockevent",
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		.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_MODE_PERIODIC,
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		.set_mode = efm32_clock_event_set_mode,
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		.set_next_event = efm32_clock_event_set_next_event,
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		.rating = 200,
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	},
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};
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static struct irqaction efm32_clock_event_irq = {
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	.name = "efm32 clockevent",
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	.flags = IRQF_TIMER,
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	.handler = efm32_clock_event_handler,
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	.dev_id = &clock_event_ddata,
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};
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static int __init efm32_clocksource_init(struct device_node *np)
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{
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	struct clk *clk;
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	void __iomem *base;
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	unsigned long rate;
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	int ret;
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	clk = of_clk_get(np, 0);
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	if (IS_ERR(clk)) {
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		ret = PTR_ERR(clk);
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		pr_err("failed to get clock for clocksource (%d)\n", ret);
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		goto err_clk_get;
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	}
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	ret = clk_prepare_enable(clk);
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	if (ret) {
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		pr_err("failed to enable timer clock for clocksource (%d)\n",
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		       ret);
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		goto err_clk_enable;
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	}
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	rate = clk_get_rate(clk);
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	base = of_iomap(np, 0);
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	if (!base) {
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		ret = -EADDRNOTAVAIL;
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		pr_err("failed to map registers for clocksource\n");
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		goto err_iomap;
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	}
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	writel_relaxed(TIMERn_CTRL_PRESC_1024 |
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		       TIMERn_CTRL_CLKSEL_PRESCHFPERCLK |
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		       TIMERn_CTRL_MODE_UP, base + TIMERn_CTRL);
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	writel_relaxed(TIMERn_CMD_START, base + TIMERn_CMD);
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	ret = clocksource_mmio_init(base + TIMERn_CNT, "efm32 timer",
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				    DIV_ROUND_CLOSEST(rate, 1024), 200, 16,
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				    clocksource_mmio_readl_up);
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	if (ret) {
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		pr_err("failed to init clocksource (%d)\n", ret);
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		goto err_clocksource_init;
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	}
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	return 0;
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err_clocksource_init:
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	iounmap(base);
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err_iomap:
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	clk_disable_unprepare(clk);
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err_clk_enable:
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	clk_put(clk);
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err_clk_get:
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	return ret;
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}
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static int __init efm32_clockevent_init(struct device_node *np)
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{
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	struct clk *clk;
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	void __iomem *base;
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	unsigned long rate;
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	int irq;
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	int ret;
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	clk = of_clk_get(np, 0);
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	if (IS_ERR(clk)) {
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		ret = PTR_ERR(clk);
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		pr_err("failed to get clock for clockevent (%d)\n", ret);
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		goto err_clk_get;
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	}
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	ret = clk_prepare_enable(clk);
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	if (ret) {
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		pr_err("failed to enable timer clock for clockevent (%d)\n",
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		       ret);
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		goto err_clk_enable;
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	}
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	rate = clk_get_rate(clk);
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	base = of_iomap(np, 0);
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	if (!base) {
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		ret = -EADDRNOTAVAIL;
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		pr_err("failed to map registers for clockevent\n");
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		goto err_iomap;
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	}
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	irq = irq_of_parse_and_map(np, 0);
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	if (!irq) {
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		ret = -ENOENT;
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		pr_err("failed to get irq for clockevent\n");
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		goto err_get_irq;
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	}
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	writel_relaxed(TIMERn_IRQ_UF, base + TIMERn_IEN);
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	clock_event_ddata.base = base;
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	clock_event_ddata.periodic_top = DIV_ROUND_CLOSEST(rate, 1024 * HZ);
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	setup_irq(irq, &efm32_clock_event_irq);
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	clockevents_config_and_register(&clock_event_ddata.evtdev,
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					DIV_ROUND_CLOSEST(rate, 1024),
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					0xf, 0xffff);
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	return 0;
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err_get_irq:
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	iounmap(base);
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err_iomap:
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	clk_disable_unprepare(clk);
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err_clk_enable:
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	clk_put(clk);
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err_clk_get:
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	return ret;
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}
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/*
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 * This function asserts that we have exactly one clocksource and one
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 * clock_event_device in the end.
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 */
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static void __init efm32_timer_init(struct device_node *np)
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{
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	static int has_clocksource, has_clockevent;
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	int ret;
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	if (!has_clocksource) {
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		ret = efm32_clocksource_init(np);
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		if (!ret) {
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			has_clocksource = 1;
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			return;
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		}
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	}
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	if (!has_clockevent) {
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		ret = efm32_clockevent_init(np);
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		if (!ret) {
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			has_clockevent = 1;
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			return;
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		}
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	}
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}
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CLOCKSOURCE_OF_DECLARE(efm32compat, "efm32,timer", efm32_timer_init);
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CLOCKSOURCE_OF_DECLARE(efm32, "energymicro,efm32-timer", efm32_timer_init);
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