03daa99ef5
Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports 16 MSI registers, but uses different IBS and SRS shift. When using MSIR1, the interrupt number is not consecutive. It is hard to use 'msi-available-ranges' to describe the ranges of the available interrupt, so MPIC v4.3 does not support this property. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> [scottwood@freescale.com: minor grammar fixes] Signed-off-by: Scott Wood <scottwood@freescale.com> |
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| .. | ||
| bindings | ||
| 00-INDEX | ||
| booting-without-of.txt | ||
| usage-model.txt | ||