fc71ff7583
Check the host's USB2 LPM capability. USB2 software LPM support is optional for xHCI 0.96 hosts. xHCI 1.0 hosts should support software LPM, and may support hardware LPM. Signed-off-by: Andiry Xu <andiry.xu@amd.com> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
154 lines
5.2 KiB
C
154 lines
5.2 KiB
C
/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* Up to 16 ms to halt an HC */
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#define XHCI_MAX_HALT_USEC (16*1000)
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/* HC not running - set to 1 when run/stop bit is cleared. */
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#define XHCI_STS_HALT (1<<0)
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/* HCCPARAMS offset from PCI base address */
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#define XHCI_HCC_PARAMS_OFFSET 0x10
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/* HCCPARAMS contains the first extended capability pointer */
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#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
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/* Command and Status registers offset from the Operational Registers address */
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#define XHCI_CMD_OFFSET 0x00
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#define XHCI_STS_OFFSET 0x04
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#define XHCI_MAX_EXT_CAPS 50
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/* Capability Register */
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/* bits 7:0 - how long is the Capabilities register */
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#define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
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/* Extended capability register fields */
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#define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
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#define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
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#define XHCI_EXT_CAPS_VAL(p) ((p)>>16)
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/* Extended capability IDs - ID 0 reserved */
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#define XHCI_EXT_CAPS_LEGACY 1
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#define XHCI_EXT_CAPS_PROTOCOL 2
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#define XHCI_EXT_CAPS_PM 3
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#define XHCI_EXT_CAPS_VIRT 4
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#define XHCI_EXT_CAPS_ROUTE 5
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/* IDs 6-9 reserved */
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#define XHCI_EXT_CAPS_DEBUG 10
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/* USB Legacy Support Capability - section 7.1.1 */
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#define XHCI_HC_BIOS_OWNED (1 << 16)
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#define XHCI_HC_OS_OWNED (1 << 24)
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/* USB Legacy Support Capability - section 7.1.1 */
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/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
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#define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
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/* USB Legacy Support Control and Status Register - section 7.1.2 */
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/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
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#define XHCI_LEGACY_CONTROL_OFFSET (0x04)
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/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
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#define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17))
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/* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
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#define XHCI_L1C (1 << 16)
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/* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
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#define XHCI_HLC (1 << 19)
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/* command register values to disable interrupts and halt the HC */
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/* start/stop HC execution - do not write unless HC is halted*/
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#define XHCI_CMD_RUN (1 << 0)
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/* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
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#define XHCI_CMD_EIE (1 << 2)
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/* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
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#define XHCI_CMD_HSEIE (1 << 3)
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/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
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#define XHCI_CMD_EWE (1 << 10)
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#define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
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/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
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#define XHCI_STS_CNR (1 << 11)
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#include <linux/io.h>
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/**
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* Return the next extended capability pointer register.
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*
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* @base PCI register base address.
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*
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* @ext_offset Offset of the 32-bit register that contains the extended
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* capabilites pointer. If searching for the first extended capability, pass
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* in XHCI_HCC_PARAMS_OFFSET. If searching for the next extended capability,
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* pass in the offset of the current extended capability register.
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*
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* Returns 0 if there is no next extended capability register or returns the register offset
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* from the PCI registers base address.
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*/
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static inline int xhci_find_next_cap_offset(void __iomem *base, int ext_offset)
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{
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u32 next;
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next = readl(base + ext_offset);
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if (ext_offset == XHCI_HCC_PARAMS_OFFSET) {
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/* Find the first extended capability */
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next = XHCI_HCC_EXT_CAPS(next);
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ext_offset = 0;
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} else {
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/* Find the next extended capability */
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next = XHCI_EXT_CAPS_NEXT(next);
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}
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if (!next)
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return 0;
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/*
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* Address calculation from offset of extended capabilities
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* (or HCCPARAMS) register - see section 5.3.6 and section 7.
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*/
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return ext_offset + (next << 2);
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}
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/**
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* Find the offset of the extended capabilities with capability ID id.
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*
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* @base PCI MMIO registers base address.
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* @ext_offset Offset from base of the first extended capability to look at,
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* or the address of HCCPARAMS.
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* @id Extended capability ID to search for.
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*
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* This uses an arbitrary limit of XHCI_MAX_EXT_CAPS extended capabilities
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* to make sure that the list doesn't contain a loop.
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*/
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static inline int xhci_find_ext_cap_by_id(void __iomem *base, int ext_offset, int id)
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{
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u32 val;
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int limit = XHCI_MAX_EXT_CAPS;
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while (ext_offset && limit > 0) {
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val = readl(base + ext_offset);
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if (XHCI_EXT_CAPS_ID(val) == id)
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break;
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ext_offset = xhci_find_next_cap_offset(base, ext_offset);
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limit--;
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}
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if (limit > 0)
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return ext_offset;
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return 0;
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}
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