1511 lines
36 KiB
C
1511 lines
36 KiB
C
/*
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* mfd.c: driver for High Speed UART device of Intel Medfield platform
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*
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* Refer pxa.c, 8250.c and some other drivers in drivers/serial/
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*
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* (C) Copyright 2010 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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/* Notes:
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* 1. DMA channel allocation: 0/1 channel are assigned to port 0,
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* 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
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* are used for RX, odd chans for TX
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*
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* 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
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* asserted, only when the HW is reset the DDCD and DDSR will
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* be triggered
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/serial_reg.h>
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#include <linux/circ_buf.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial_mfd.h>
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#include <linux/dma-mapping.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/debugfs.h>
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#include <linux/pm_runtime.h>
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#define HSU_DMA_BUF_SIZE 2048
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#define chan_readl(chan, offset) readl(chan->reg + offset)
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#define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
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#define mfd_readl(obj, offset) readl(obj->reg + offset)
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#define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
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static int hsu_dma_enable;
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module_param(hsu_dma_enable, int, 0);
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MODULE_PARM_DESC(hsu_dma_enable,
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"It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode.");
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struct hsu_dma_buffer {
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u8 *buf;
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dma_addr_t dma_addr;
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u32 dma_size;
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u32 ofs;
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};
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struct hsu_dma_chan {
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u32 id;
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enum dma_data_direction dirt;
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struct uart_hsu_port *uport;
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void __iomem *reg;
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};
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struct uart_hsu_port {
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struct uart_port port;
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unsigned char ier;
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unsigned char lcr;
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unsigned char mcr;
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unsigned int lsr_break_flag;
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char name[12];
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int index;
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struct device *dev;
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struct hsu_dma_chan *txc;
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struct hsu_dma_chan *rxc;
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struct hsu_dma_buffer txbuf;
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struct hsu_dma_buffer rxbuf;
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int use_dma; /* flag for DMA/PIO */
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int running;
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int dma_tx_on;
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};
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/* Top level data structure of HSU */
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struct hsu_port {
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void __iomem *reg;
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unsigned long paddr;
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unsigned long iolen;
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u32 irq;
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struct uart_hsu_port port[3];
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struct hsu_dma_chan chans[10];
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struct dentry *debugfs;
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};
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static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
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{
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unsigned int val;
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if (offset > UART_MSR) {
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offset <<= 2;
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val = readl(up->port.membase + offset);
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} else
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val = (unsigned int)readb(up->port.membase + offset);
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return val;
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}
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static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
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{
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if (offset > UART_MSR) {
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offset <<= 2;
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writel(value, up->port.membase + offset);
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} else {
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unsigned char val = value & 0xff;
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writeb(val, up->port.membase + offset);
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}
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}
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#ifdef CONFIG_DEBUG_FS
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#define HSU_REGS_BUFSIZE 1024
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static int hsu_show_regs_open(struct inode *inode, struct file *file)
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{
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file->private_data = inode->i_private;
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return 0;
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}
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static ssize_t port_show_regs(struct file *file, char __user *user_buf,
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size_t count, loff_t *ppos)
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{
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struct uart_hsu_port *up = file->private_data;
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char *buf;
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u32 len = 0;
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ssize_t ret;
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buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
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if (!buf)
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return 0;
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"MFD HSU port[%d] regs:\n", up->index);
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"=================================\n");
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"IER: \t\t0x%08x\n", serial_in(up, UART_IER));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"PS: \t\t0x%08x\n", serial_in(up, UART_PS));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
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if (len > HSU_REGS_BUFSIZE)
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len = HSU_REGS_BUFSIZE;
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ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
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kfree(buf);
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return ret;
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}
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static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
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size_t count, loff_t *ppos)
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{
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struct hsu_dma_chan *chan = file->private_data;
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char *buf;
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u32 len = 0;
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ssize_t ret;
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buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
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if (!buf)
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return 0;
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"MFD HSU DMA channel [%d] regs:\n", chan->id);
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"=================================\n");
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
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len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
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"D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
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if (len > HSU_REGS_BUFSIZE)
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len = HSU_REGS_BUFSIZE;
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ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
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kfree(buf);
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return ret;
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}
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static const struct file_operations port_regs_ops = {
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.owner = THIS_MODULE,
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.open = hsu_show_regs_open,
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.read = port_show_regs,
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.llseek = default_llseek,
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};
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static const struct file_operations dma_regs_ops = {
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.owner = THIS_MODULE,
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.open = hsu_show_regs_open,
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.read = dma_show_regs,
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.llseek = default_llseek,
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};
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static int hsu_debugfs_init(struct hsu_port *hsu)
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{
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int i;
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char name[32];
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hsu->debugfs = debugfs_create_dir("hsu", NULL);
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if (!hsu->debugfs)
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return -ENOMEM;
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for (i = 0; i < 3; i++) {
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snprintf(name, sizeof(name), "port_%d_regs", i);
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debugfs_create_file(name, S_IFREG | S_IRUGO,
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hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
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}
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for (i = 0; i < 6; i++) {
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snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
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debugfs_create_file(name, S_IFREG | S_IRUGO,
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hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
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}
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return 0;
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}
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static void hsu_debugfs_remove(struct hsu_port *hsu)
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{
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if (hsu->debugfs)
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debugfs_remove_recursive(hsu->debugfs);
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}
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#else
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static inline int hsu_debugfs_init(struct hsu_port *hsu)
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{
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return 0;
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}
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static inline void hsu_debugfs_remove(struct hsu_port *hsu)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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static void serial_hsu_enable_ms(struct uart_port *port)
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{
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struct uart_hsu_port *up =
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container_of(port, struct uart_hsu_port, port);
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up->ier |= UART_IER_MSI;
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serial_out(up, UART_IER, up->ier);
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}
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void hsu_dma_tx(struct uart_hsu_port *up)
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{
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struct circ_buf *xmit = &up->port.state->xmit;
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struct hsu_dma_buffer *dbuf = &up->txbuf;
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int count;
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/* test_and_set_bit may be better, but anyway it's in lock protected mode */
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if (up->dma_tx_on)
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return;
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/* Update the circ buf info */
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xmit->tail += dbuf->ofs;
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xmit->tail &= UART_XMIT_SIZE - 1;
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up->port.icount.tx += dbuf->ofs;
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dbuf->ofs = 0;
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/* Disable the channel */
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chan_writel(up->txc, HSU_CH_CR, 0x0);
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if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
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dma_sync_single_for_device(up->port.dev,
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dbuf->dma_addr,
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dbuf->dma_size,
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DMA_TO_DEVICE);
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count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
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dbuf->ofs = count;
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/* Reprogram the channel */
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chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
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chan_writel(up->txc, HSU_CH_D0TSR, count);
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/* Reenable the channel */
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chan_writel(up->txc, HSU_CH_DCR, 0x1
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| (0x1 << 8)
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| (0x1 << 16)
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| (0x1 << 24));
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up->dma_tx_on = 1;
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chan_writel(up->txc, HSU_CH_CR, 0x1);
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&up->port);
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}
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/* The buffer is already cache coherent */
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void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
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{
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dbuf->ofs = 0;
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chan_writel(rxc, HSU_CH_BSR, 32);
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chan_writel(rxc, HSU_CH_MOTSR, 4);
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chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
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chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
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chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
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| (0x1 << 16)
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| (0x1 << 24) /* timeout bit, see HSU Errata 1 */
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);
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chan_writel(rxc, HSU_CH_CR, 0x3);
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}
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/* Protected by spin_lock_irqsave(port->lock) */
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static void serial_hsu_start_tx(struct uart_port *port)
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{
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struct uart_hsu_port *up =
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container_of(port, struct uart_hsu_port, port);
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if (up->use_dma) {
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hsu_dma_tx(up);
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} else if (!(up->ier & UART_IER_THRI)) {
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up->ier |= UART_IER_THRI;
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serial_out(up, UART_IER, up->ier);
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}
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}
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static void serial_hsu_stop_tx(struct uart_port *port)
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{
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struct uart_hsu_port *up =
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container_of(port, struct uart_hsu_port, port);
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struct hsu_dma_chan *txc = up->txc;
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if (up->use_dma)
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chan_writel(txc, HSU_CH_CR, 0x0);
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else if (up->ier & UART_IER_THRI) {
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up->ier &= ~UART_IER_THRI;
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serial_out(up, UART_IER, up->ier);
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}
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}
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/* This is always called in spinlock protected mode, so
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* modify timeout timer is safe here */
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void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
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{
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struct hsu_dma_buffer *dbuf = &up->rxbuf;
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struct hsu_dma_chan *chan = up->rxc;
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struct uart_port *port = &up->port;
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struct tty_struct *tty = port->state->port.tty;
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int count;
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if (!tty)
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return;
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/*
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* First need to know how many is already transferred,
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* then check if its a timeout DMA irq, and return
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* the trail bytes out, push them up and reenable the
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* channel
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*/
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/* Timeout IRQ, need wait some time, see Errata 2 */
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if (int_sts & 0xf00)
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udelay(2);
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/* Stop the channel */
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chan_writel(chan, HSU_CH_CR, 0x0);
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count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
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if (!count) {
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/* Restart the channel before we leave */
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chan_writel(chan, HSU_CH_CR, 0x3);
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return;
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}
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dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
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dbuf->dma_size, DMA_FROM_DEVICE);
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/*
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* Head will only wrap around when we recycle
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* the DMA buffer, and when that happens, we
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* explicitly set tail to 0. So head will
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* always be greater than tail.
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*/
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tty_insert_flip_string(tty, dbuf->buf, count);
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port->icount.rx += count;
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dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
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dbuf->dma_size, DMA_FROM_DEVICE);
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/* Reprogram the channel */
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chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
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chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
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chan_writel(chan, HSU_CH_DCR, 0x1
|
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| (0x1 << 8)
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| (0x1 << 16)
|
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| (0x1 << 24) /* timeout bit, see HSU Errata 1 */
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);
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tty_flip_buffer_push(tty);
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chan_writel(chan, HSU_CH_CR, 0x3);
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}
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static void serial_hsu_stop_rx(struct uart_port *port)
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{
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struct uart_hsu_port *up =
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container_of(port, struct uart_hsu_port, port);
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struct hsu_dma_chan *chan = up->rxc;
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if (up->use_dma)
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chan_writel(chan, HSU_CH_CR, 0x2);
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else {
|
|
up->ier &= ~UART_IER_RLSI;
|
|
up->port.read_status_mask &= ~UART_LSR_DR;
|
|
serial_out(up, UART_IER, up->ier);
|
|
}
|
|
}
|
|
|
|
static inline void receive_chars(struct uart_hsu_port *up, int *status)
|
|
{
|
|
struct tty_struct *tty = up->port.state->port.tty;
|
|
unsigned int ch, flag;
|
|
unsigned int max_count = 256;
|
|
|
|
if (!tty)
|
|
return;
|
|
|
|
do {
|
|
ch = serial_in(up, UART_RX);
|
|
flag = TTY_NORMAL;
|
|
up->port.icount.rx++;
|
|
|
|
if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
|
|
UART_LSR_FE | UART_LSR_OE))) {
|
|
|
|
dev_warn(up->dev, "We really rush into ERR/BI case"
|
|
"status = 0x%02x", *status);
|
|
/* For statistics only */
|
|
if (*status & UART_LSR_BI) {
|
|
*status &= ~(UART_LSR_FE | UART_LSR_PE);
|
|
up->port.icount.brk++;
|
|
/*
|
|
* We do the SysRQ and SAK checking
|
|
* here because otherwise the break
|
|
* may get masked by ignore_status_mask
|
|
* or read_status_mask.
|
|
*/
|
|
if (uart_handle_break(&up->port))
|
|
goto ignore_char;
|
|
} else if (*status & UART_LSR_PE)
|
|
up->port.icount.parity++;
|
|
else if (*status & UART_LSR_FE)
|
|
up->port.icount.frame++;
|
|
if (*status & UART_LSR_OE)
|
|
up->port.icount.overrun++;
|
|
|
|
/* Mask off conditions which should be ignored. */
|
|
*status &= up->port.read_status_mask;
|
|
|
|
#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
|
|
if (up->port.cons &&
|
|
up->port.cons->index == up->port.line) {
|
|
/* Recover the break flag from console xmit */
|
|
*status |= up->lsr_break_flag;
|
|
up->lsr_break_flag = 0;
|
|
}
|
|
#endif
|
|
if (*status & UART_LSR_BI) {
|
|
flag = TTY_BREAK;
|
|
} else if (*status & UART_LSR_PE)
|
|
flag = TTY_PARITY;
|
|
else if (*status & UART_LSR_FE)
|
|
flag = TTY_FRAME;
|
|
}
|
|
|
|
if (uart_handle_sysrq_char(&up->port, ch))
|
|
goto ignore_char;
|
|
|
|
uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
|
|
ignore_char:
|
|
*status = serial_in(up, UART_LSR);
|
|
} while ((*status & UART_LSR_DR) && max_count--);
|
|
tty_flip_buffer_push(tty);
|
|
}
|
|
|
|
static void transmit_chars(struct uart_hsu_port *up)
|
|
{
|
|
struct circ_buf *xmit = &up->port.state->xmit;
|
|
int count;
|
|
|
|
if (up->port.x_char) {
|
|
serial_out(up, UART_TX, up->port.x_char);
|
|
up->port.icount.tx++;
|
|
up->port.x_char = 0;
|
|
return;
|
|
}
|
|
if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
|
|
serial_hsu_stop_tx(&up->port);
|
|
return;
|
|
}
|
|
|
|
/* The IRQ is for TX FIFO half-empty */
|
|
count = up->port.fifosize / 2;
|
|
|
|
do {
|
|
serial_out(up, UART_TX, xmit->buf[xmit->tail]);
|
|
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
|
|
|
|
up->port.icount.tx++;
|
|
if (uart_circ_empty(xmit))
|
|
break;
|
|
} while (--count > 0);
|
|
|
|
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
|
uart_write_wakeup(&up->port);
|
|
|
|
if (uart_circ_empty(xmit))
|
|
serial_hsu_stop_tx(&up->port);
|
|
}
|
|
|
|
static inline void check_modem_status(struct uart_hsu_port *up)
|
|
{
|
|
int status;
|
|
|
|
status = serial_in(up, UART_MSR);
|
|
|
|
if ((status & UART_MSR_ANY_DELTA) == 0)
|
|
return;
|
|
|
|
if (status & UART_MSR_TERI)
|
|
up->port.icount.rng++;
|
|
if (status & UART_MSR_DDSR)
|
|
up->port.icount.dsr++;
|
|
/* We may only get DDCD when HW init and reset */
|
|
if (status & UART_MSR_DDCD)
|
|
uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
|
|
/* Will start/stop_tx accordingly */
|
|
if (status & UART_MSR_DCTS)
|
|
uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
|
|
|
|
wake_up_interruptible(&up->port.state->port.delta_msr_wait);
|
|
}
|
|
|
|
/*
|
|
* This handles the interrupt from one port.
|
|
*/
|
|
static irqreturn_t port_irq(int irq, void *dev_id)
|
|
{
|
|
struct uart_hsu_port *up = dev_id;
|
|
unsigned int iir, lsr;
|
|
unsigned long flags;
|
|
|
|
if (unlikely(!up->running))
|
|
return IRQ_NONE;
|
|
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
if (up->use_dma) {
|
|
lsr = serial_in(up, UART_LSR);
|
|
if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
|
|
UART_LSR_FE | UART_LSR_OE)))
|
|
dev_warn(up->dev,
|
|
"Got lsr irq while using DMA, lsr = 0x%2x\n",
|
|
lsr);
|
|
check_modem_status(up);
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
iir = serial_in(up, UART_IIR);
|
|
if (iir & UART_IIR_NO_INT) {
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
lsr = serial_in(up, UART_LSR);
|
|
if (lsr & UART_LSR_DR)
|
|
receive_chars(up, &lsr);
|
|
check_modem_status(up);
|
|
|
|
/* lsr will be renewed during the receive_chars */
|
|
if (lsr & UART_LSR_THRE)
|
|
transmit_chars(up);
|
|
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static inline void dma_chan_irq(struct hsu_dma_chan *chan)
|
|
{
|
|
struct uart_hsu_port *up = chan->uport;
|
|
unsigned long flags;
|
|
u32 int_sts;
|
|
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
|
|
if (!up->use_dma || !up->running)
|
|
goto exit;
|
|
|
|
/*
|
|
* No matter what situation, need read clear the IRQ status
|
|
* There is a bug, see Errata 5, HSD 2900918
|
|
*/
|
|
int_sts = chan_readl(chan, HSU_CH_SR);
|
|
|
|
/* Rx channel */
|
|
if (chan->dirt == DMA_FROM_DEVICE)
|
|
hsu_dma_rx(up, int_sts);
|
|
|
|
/* Tx channel */
|
|
if (chan->dirt == DMA_TO_DEVICE) {
|
|
chan_writel(chan, HSU_CH_CR, 0x0);
|
|
up->dma_tx_on = 0;
|
|
hsu_dma_tx(up);
|
|
}
|
|
|
|
exit:
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
return;
|
|
}
|
|
|
|
static irqreturn_t dma_irq(int irq, void *dev_id)
|
|
{
|
|
struct hsu_port *hsu = dev_id;
|
|
u32 int_sts, i;
|
|
|
|
int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
|
|
|
|
/* Currently we only have 6 channels may be used */
|
|
for (i = 0; i < 6; i++) {
|
|
if (int_sts & 0x1)
|
|
dma_chan_irq(&hsu->chans[i]);
|
|
int_sts >>= 1;
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static unsigned int serial_hsu_tx_empty(struct uart_port *port)
|
|
{
|
|
struct uart_hsu_port *up =
|
|
container_of(port, struct uart_hsu_port, port);
|
|
unsigned long flags;
|
|
unsigned int ret;
|
|
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
|
|
{
|
|
struct uart_hsu_port *up =
|
|
container_of(port, struct uart_hsu_port, port);
|
|
unsigned char status;
|
|
unsigned int ret;
|
|
|
|
status = serial_in(up, UART_MSR);
|
|
|
|
ret = 0;
|
|
if (status & UART_MSR_DCD)
|
|
ret |= TIOCM_CAR;
|
|
if (status & UART_MSR_RI)
|
|
ret |= TIOCM_RNG;
|
|
if (status & UART_MSR_DSR)
|
|
ret |= TIOCM_DSR;
|
|
if (status & UART_MSR_CTS)
|
|
ret |= TIOCM_CTS;
|
|
return ret;
|
|
}
|
|
|
|
static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
|
{
|
|
struct uart_hsu_port *up =
|
|
container_of(port, struct uart_hsu_port, port);
|
|
unsigned char mcr = 0;
|
|
|
|
if (mctrl & TIOCM_RTS)
|
|
mcr |= UART_MCR_RTS;
|
|
if (mctrl & TIOCM_DTR)
|
|
mcr |= UART_MCR_DTR;
|
|
if (mctrl & TIOCM_OUT1)
|
|
mcr |= UART_MCR_OUT1;
|
|
if (mctrl & TIOCM_OUT2)
|
|
mcr |= UART_MCR_OUT2;
|
|
if (mctrl & TIOCM_LOOP)
|
|
mcr |= UART_MCR_LOOP;
|
|
|
|
mcr |= up->mcr;
|
|
|
|
serial_out(up, UART_MCR, mcr);
|
|
}
|
|
|
|
static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
|
|
{
|
|
struct uart_hsu_port *up =
|
|
container_of(port, struct uart_hsu_port, port);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
if (break_state == -1)
|
|
up->lcr |= UART_LCR_SBC;
|
|
else
|
|
up->lcr &= ~UART_LCR_SBC;
|
|
serial_out(up, UART_LCR, up->lcr);
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
}
|
|
|
|
/*
|
|
* What special to do:
|
|
* 1. chose the 64B fifo mode
|
|
* 2. start dma or pio depends on configuration
|
|
* 3. we only allocate dma memory when needed
|
|
*/
|
|
static int serial_hsu_startup(struct uart_port *port)
|
|
{
|
|
struct uart_hsu_port *up =
|
|
container_of(port, struct uart_hsu_port, port);
|
|
unsigned long flags;
|
|
|
|
pm_runtime_get_sync(up->dev);
|
|
|
|
/*
|
|
* Clear the FIFO buffers and disable them.
|
|
* (they will be reenabled in set_termios())
|
|
*/
|
|
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
|
|
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
|
|
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
|
|
serial_out(up, UART_FCR, 0);
|
|
|
|
/* Clear the interrupt registers. */
|
|
(void) serial_in(up, UART_LSR);
|
|
(void) serial_in(up, UART_RX);
|
|
(void) serial_in(up, UART_IIR);
|
|
(void) serial_in(up, UART_MSR);
|
|
|
|
/* Now, initialize the UART, default is 8n1 */
|
|
serial_out(up, UART_LCR, UART_LCR_WLEN8);
|
|
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
|
|
up->port.mctrl |= TIOCM_OUT2;
|
|
serial_hsu_set_mctrl(&up->port, up->port.mctrl);
|
|
|
|
/*
|
|
* Finally, enable interrupts. Note: Modem status interrupts
|
|
* are set via set_termios(), which will be occurring imminently
|
|
* anyway, so we don't enable them here.
|
|
*/
|
|
if (!up->use_dma)
|
|
up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
|
|
else
|
|
up->ier = 0;
|
|
serial_out(up, UART_IER, up->ier);
|
|
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
|
|
/* DMA init */
|
|
if (up->use_dma) {
|
|
struct hsu_dma_buffer *dbuf;
|
|
struct circ_buf *xmit = &port->state->xmit;
|
|
|
|
up->dma_tx_on = 0;
|
|
|
|
/* First allocate the RX buffer */
|
|
dbuf = &up->rxbuf;
|
|
dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
|
|
if (!dbuf->buf) {
|
|
up->use_dma = 0;
|
|
goto exit;
|
|
}
|
|
dbuf->dma_addr = dma_map_single(port->dev,
|
|
dbuf->buf,
|
|
HSU_DMA_BUF_SIZE,
|
|
DMA_FROM_DEVICE);
|
|
dbuf->dma_size = HSU_DMA_BUF_SIZE;
|
|
|
|
/* Start the RX channel right now */
|
|
hsu_dma_start_rx_chan(up->rxc, dbuf);
|
|
|
|
/* Next init the TX DMA */
|
|
dbuf = &up->txbuf;
|
|
dbuf->buf = xmit->buf;
|
|
dbuf->dma_addr = dma_map_single(port->dev,
|
|
dbuf->buf,
|
|
UART_XMIT_SIZE,
|
|
DMA_TO_DEVICE);
|
|
dbuf->dma_size = UART_XMIT_SIZE;
|
|
|
|
/* This should not be changed all around */
|
|
chan_writel(up->txc, HSU_CH_BSR, 32);
|
|
chan_writel(up->txc, HSU_CH_MOTSR, 4);
|
|
dbuf->ofs = 0;
|
|
}
|
|
|
|
exit:
|
|
/* And clear the interrupt registers again for luck. */
|
|
(void) serial_in(up, UART_LSR);
|
|
(void) serial_in(up, UART_RX);
|
|
(void) serial_in(up, UART_IIR);
|
|
(void) serial_in(up, UART_MSR);
|
|
|
|
up->running = 1;
|
|
return 0;
|
|
}
|
|
|
|
static void serial_hsu_shutdown(struct uart_port *port)
|
|
{
|
|
struct uart_hsu_port *up =
|
|
container_of(port, struct uart_hsu_port, port);
|
|
unsigned long flags;
|
|
|
|
/* Disable interrupts from this port */
|
|
up->ier = 0;
|
|
serial_out(up, UART_IER, 0);
|
|
up->running = 0;
|
|
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
up->port.mctrl &= ~TIOCM_OUT2;
|
|
serial_hsu_set_mctrl(&up->port, up->port.mctrl);
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
|
|
/* Disable break condition and FIFOs */
|
|
serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
|
|
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
|
|
UART_FCR_CLEAR_RCVR |
|
|
UART_FCR_CLEAR_XMIT);
|
|
serial_out(up, UART_FCR, 0);
|
|
|
|
pm_runtime_put(up->dev);
|
|
}
|
|
|
|
static void
|
|
serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
|
|
struct ktermios *old)
|
|
{
|
|
struct uart_hsu_port *up =
|
|
container_of(port, struct uart_hsu_port, port);
|
|
unsigned char cval, fcr = 0;
|
|
unsigned long flags;
|
|
unsigned int baud, quot;
|
|
u32 ps, mul;
|
|
|
|
switch (termios->c_cflag & CSIZE) {
|
|
case CS5:
|
|
cval = UART_LCR_WLEN5;
|
|
break;
|
|
case CS6:
|
|
cval = UART_LCR_WLEN6;
|
|
break;
|
|
case CS7:
|
|
cval = UART_LCR_WLEN7;
|
|
break;
|
|
default:
|
|
case CS8:
|
|
cval = UART_LCR_WLEN8;
|
|
break;
|
|
}
|
|
|
|
/* CMSPAR isn't supported by this driver */
|
|
termios->c_cflag &= ~CMSPAR;
|
|
|
|
if (termios->c_cflag & CSTOPB)
|
|
cval |= UART_LCR_STOP;
|
|
if (termios->c_cflag & PARENB)
|
|
cval |= UART_LCR_PARITY;
|
|
if (!(termios->c_cflag & PARODD))
|
|
cval |= UART_LCR_EPAR;
|
|
|
|
/*
|
|
* The base clk is 50Mhz, and the baud rate come from:
|
|
* baud = 50M * MUL / (DIV * PS * DLAB)
|
|
*
|
|
* For those basic low baud rate we can get the direct
|
|
* scalar from 2746800, like 115200 = 2746800/24. For those
|
|
* higher baud rate, we handle them case by case, mainly by
|
|
* adjusting the MUL/PS registers, and DIV register is kept
|
|
* as default value 0x3d09 to make things simple
|
|
*/
|
|
baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
|
|
|
|
quot = 1;
|
|
ps = 0x10;
|
|
mul = 0x3600;
|
|
switch (baud) {
|
|
case 3500000:
|
|
mul = 0x3345;
|
|
ps = 0xC;
|
|
break;
|
|
case 1843200:
|
|
mul = 0x2400;
|
|
break;
|
|
case 3000000:
|
|
case 2500000:
|
|
case 2000000:
|
|
case 1500000:
|
|
case 1000000:
|
|
case 500000:
|
|
/* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */
|
|
mul = baud / 500000 * 0x9C4;
|
|
break;
|
|
default:
|
|
/* Use uart_get_divisor to get quot for other baud rates */
|
|
quot = 0;
|
|
}
|
|
|
|
if (!quot)
|
|
quot = uart_get_divisor(port, baud);
|
|
|
|
if ((up->port.uartclk / quot) < (2400 * 16))
|
|
fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
|
|
else if ((up->port.uartclk / quot) < (230400 * 16))
|
|
fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
|
|
else
|
|
fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
|
|
|
|
fcr |= UART_FCR_HSU_64B_FIFO;
|
|
|
|
/*
|
|
* Ok, we're now changing the port state. Do it with
|
|
* interrupts disabled.
|
|
*/
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
|
|
/* Update the per-port timeout */
|
|
uart_update_timeout(port, termios->c_cflag, baud);
|
|
|
|
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
|
|
if (termios->c_iflag & INPCK)
|
|
up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
|
|
if (termios->c_iflag & (BRKINT | PARMRK))
|
|
up->port.read_status_mask |= UART_LSR_BI;
|
|
|
|
/* Characters to ignore */
|
|
up->port.ignore_status_mask = 0;
|
|
if (termios->c_iflag & IGNPAR)
|
|
up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
|
|
if (termios->c_iflag & IGNBRK) {
|
|
up->port.ignore_status_mask |= UART_LSR_BI;
|
|
/*
|
|
* If we're ignoring parity and break indicators,
|
|
* ignore overruns too (for real raw support).
|
|
*/
|
|
if (termios->c_iflag & IGNPAR)
|
|
up->port.ignore_status_mask |= UART_LSR_OE;
|
|
}
|
|
|
|
/* Ignore all characters if CREAD is not set */
|
|
if ((termios->c_cflag & CREAD) == 0)
|
|
up->port.ignore_status_mask |= UART_LSR_DR;
|
|
|
|
/*
|
|
* CTS flow control flag and modem status interrupts, disable
|
|
* MSI by default
|
|
*/
|
|
up->ier &= ~UART_IER_MSI;
|
|
if (UART_ENABLE_MS(&up->port, termios->c_cflag))
|
|
up->ier |= UART_IER_MSI;
|
|
|
|
serial_out(up, UART_IER, up->ier);
|
|
|
|
if (termios->c_cflag & CRTSCTS)
|
|
up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
|
|
else
|
|
up->mcr &= ~UART_MCR_AFE;
|
|
|
|
serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
|
|
serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
|
|
serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
|
|
serial_out(up, UART_LCR, cval); /* reset DLAB */
|
|
serial_out(up, UART_MUL, mul); /* set MUL */
|
|
serial_out(up, UART_PS, ps); /* set PS */
|
|
up->lcr = cval; /* Save LCR */
|
|
serial_hsu_set_mctrl(&up->port, up->port.mctrl);
|
|
serial_out(up, UART_FCR, fcr);
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
}
|
|
|
|
static void
|
|
serial_hsu_pm(struct uart_port *port, unsigned int state,
|
|
unsigned int oldstate)
|
|
{
|
|
}
|
|
|
|
static void serial_hsu_release_port(struct uart_port *port)
|
|
{
|
|
}
|
|
|
|
static int serial_hsu_request_port(struct uart_port *port)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void serial_hsu_config_port(struct uart_port *port, int flags)
|
|
{
|
|
struct uart_hsu_port *up =
|
|
container_of(port, struct uart_hsu_port, port);
|
|
up->port.type = PORT_MFD;
|
|
}
|
|
|
|
static int
|
|
serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
|
|
{
|
|
/* We don't want the core code to modify any port params */
|
|
return -EINVAL;
|
|
}
|
|
|
|
static const char *
|
|
serial_hsu_type(struct uart_port *port)
|
|
{
|
|
struct uart_hsu_port *up =
|
|
container_of(port, struct uart_hsu_port, port);
|
|
return up->name;
|
|
}
|
|
|
|
/* Mainly for uart console use */
|
|
static struct uart_hsu_port *serial_hsu_ports[3];
|
|
static struct uart_driver serial_hsu_reg;
|
|
|
|
#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
|
|
|
|
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
|
|
|
|
/* Wait for transmitter & holding register to empty */
|
|
static inline void wait_for_xmitr(struct uart_hsu_port *up)
|
|
{
|
|
unsigned int status, tmout = 1000;
|
|
|
|
/* Wait up to 1ms for the character to be sent. */
|
|
do {
|
|
status = serial_in(up, UART_LSR);
|
|
|
|
if (status & UART_LSR_BI)
|
|
up->lsr_break_flag = UART_LSR_BI;
|
|
|
|
if (--tmout == 0)
|
|
break;
|
|
udelay(1);
|
|
} while (!(status & BOTH_EMPTY));
|
|
|
|
/* Wait up to 1s for flow control if necessary */
|
|
if (up->port.flags & UPF_CONS_FLOW) {
|
|
tmout = 1000000;
|
|
while (--tmout &&
|
|
((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
|
|
udelay(1);
|
|
}
|
|
}
|
|
|
|
static void serial_hsu_console_putchar(struct uart_port *port, int ch)
|
|
{
|
|
struct uart_hsu_port *up =
|
|
container_of(port, struct uart_hsu_port, port);
|
|
|
|
wait_for_xmitr(up);
|
|
serial_out(up, UART_TX, ch);
|
|
}
|
|
|
|
/*
|
|
* Print a string to the serial port trying not to disturb
|
|
* any possible real use of the port...
|
|
*
|
|
* The console_lock must be held when we get here.
|
|
*/
|
|
static void
|
|
serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
|
|
{
|
|
struct uart_hsu_port *up = serial_hsu_ports[co->index];
|
|
unsigned long flags;
|
|
unsigned int ier;
|
|
int locked = 1;
|
|
|
|
local_irq_save(flags);
|
|
if (up->port.sysrq)
|
|
locked = 0;
|
|
else if (oops_in_progress) {
|
|
locked = spin_trylock(&up->port.lock);
|
|
} else
|
|
spin_lock(&up->port.lock);
|
|
|
|
/* First save the IER then disable the interrupts */
|
|
ier = serial_in(up, UART_IER);
|
|
serial_out(up, UART_IER, 0);
|
|
|
|
uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
|
|
|
|
/*
|
|
* Finally, wait for transmitter to become empty
|
|
* and restore the IER
|
|
*/
|
|
wait_for_xmitr(up);
|
|
serial_out(up, UART_IER, ier);
|
|
|
|
if (locked)
|
|
spin_unlock(&up->port.lock);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static struct console serial_hsu_console;
|
|
|
|
static int __init
|
|
serial_hsu_console_setup(struct console *co, char *options)
|
|
{
|
|
struct uart_hsu_port *up;
|
|
int baud = 115200;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
if (co->index == -1 || co->index >= serial_hsu_reg.nr)
|
|
co->index = 0;
|
|
up = serial_hsu_ports[co->index];
|
|
if (!up)
|
|
return -ENODEV;
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
|
|
return uart_set_options(&up->port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct console serial_hsu_console = {
|
|
.name = "ttyMFD",
|
|
.write = serial_hsu_console_write,
|
|
.device = uart_console_device,
|
|
.setup = serial_hsu_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &serial_hsu_reg,
|
|
};
|
|
|
|
#define SERIAL_HSU_CONSOLE (&serial_hsu_console)
|
|
#else
|
|
#define SERIAL_HSU_CONSOLE NULL
|
|
#endif
|
|
|
|
struct uart_ops serial_hsu_pops = {
|
|
.tx_empty = serial_hsu_tx_empty,
|
|
.set_mctrl = serial_hsu_set_mctrl,
|
|
.get_mctrl = serial_hsu_get_mctrl,
|
|
.stop_tx = serial_hsu_stop_tx,
|
|
.start_tx = serial_hsu_start_tx,
|
|
.stop_rx = serial_hsu_stop_rx,
|
|
.enable_ms = serial_hsu_enable_ms,
|
|
.break_ctl = serial_hsu_break_ctl,
|
|
.startup = serial_hsu_startup,
|
|
.shutdown = serial_hsu_shutdown,
|
|
.set_termios = serial_hsu_set_termios,
|
|
.pm = serial_hsu_pm,
|
|
.type = serial_hsu_type,
|
|
.release_port = serial_hsu_release_port,
|
|
.request_port = serial_hsu_request_port,
|
|
.config_port = serial_hsu_config_port,
|
|
.verify_port = serial_hsu_verify_port,
|
|
};
|
|
|
|
static struct uart_driver serial_hsu_reg = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "MFD serial",
|
|
.dev_name = "ttyMFD",
|
|
.major = TTY_MAJOR,
|
|
.minor = 128,
|
|
.nr = 3,
|
|
.cons = SERIAL_HSU_CONSOLE,
|
|
};
|
|
|
|
#ifdef CONFIG_PM
|
|
static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
|
|
{
|
|
void *priv = pci_get_drvdata(pdev);
|
|
struct uart_hsu_port *up;
|
|
|
|
/* Make sure this is not the internal dma controller */
|
|
if (priv && (pdev->device != 0x081E)) {
|
|
up = priv;
|
|
uart_suspend_port(&serial_hsu_reg, &up->port);
|
|
}
|
|
|
|
pci_save_state(pdev);
|
|
pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
|
return 0;
|
|
}
|
|
|
|
static int serial_hsu_resume(struct pci_dev *pdev)
|
|
{
|
|
void *priv = pci_get_drvdata(pdev);
|
|
struct uart_hsu_port *up;
|
|
int ret;
|
|
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
pci_restore_state(pdev);
|
|
|
|
ret = pci_enable_device(pdev);
|
|
if (ret)
|
|
dev_warn(&pdev->dev,
|
|
"HSU: can't re-enable device, try to continue\n");
|
|
|
|
if (priv && (pdev->device != 0x081E)) {
|
|
up = priv;
|
|
uart_resume_port(&serial_hsu_reg, &up->port);
|
|
}
|
|
return 0;
|
|
}
|
|
#else
|
|
#define serial_hsu_suspend NULL
|
|
#define serial_hsu_resume NULL
|
|
#endif
|
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
static int serial_hsu_runtime_idle(struct device *dev)
|
|
{
|
|
int err;
|
|
|
|
err = pm_schedule_suspend(dev, 500);
|
|
if (err)
|
|
return -EBUSY;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int serial_hsu_runtime_suspend(struct device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int serial_hsu_runtime_resume(struct device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
#else
|
|
#define serial_hsu_runtime_idle NULL
|
|
#define serial_hsu_runtime_suspend NULL
|
|
#define serial_hsu_runtime_resume NULL
|
|
#endif
|
|
|
|
static const struct dev_pm_ops serial_hsu_pm_ops = {
|
|
.runtime_suspend = serial_hsu_runtime_suspend,
|
|
.runtime_resume = serial_hsu_runtime_resume,
|
|
.runtime_idle = serial_hsu_runtime_idle,
|
|
};
|
|
|
|
/* temp global pointer before we settle down on using one or four PCI dev */
|
|
static struct hsu_port *phsu;
|
|
|
|
static int serial_hsu_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
struct uart_hsu_port *uport;
|
|
int index, ret;
|
|
|
|
printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
|
|
pdev->vendor, pdev->device);
|
|
|
|
switch (pdev->device) {
|
|
case 0x081B:
|
|
index = 0;
|
|
break;
|
|
case 0x081C:
|
|
index = 1;
|
|
break;
|
|
case 0x081D:
|
|
index = 2;
|
|
break;
|
|
case 0x081E:
|
|
/* internal DMA controller */
|
|
index = 3;
|
|
break;
|
|
default:
|
|
dev_err(&pdev->dev, "HSU: out of index!");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = pci_enable_device(pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (index == 3) {
|
|
/* DMA controller */
|
|
ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "can not get IRQ\n");
|
|
goto err_disable;
|
|
}
|
|
pci_set_drvdata(pdev, phsu);
|
|
} else {
|
|
/* UART port 0~2 */
|
|
uport = &phsu->port[index];
|
|
uport->port.irq = pdev->irq;
|
|
uport->port.dev = &pdev->dev;
|
|
uport->dev = &pdev->dev;
|
|
|
|
ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "can not get IRQ\n");
|
|
goto err_disable;
|
|
}
|
|
uart_add_one_port(&serial_hsu_reg, &uport->port);
|
|
|
|
pci_set_drvdata(pdev, uport);
|
|
}
|
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
pm_runtime_allow(&pdev->dev);
|
|
|
|
return 0;
|
|
|
|
err_disable:
|
|
pci_disable_device(pdev);
|
|
return ret;
|
|
}
|
|
|
|
static void hsu_global_init(void)
|
|
{
|
|
struct hsu_port *hsu;
|
|
struct uart_hsu_port *uport;
|
|
struct hsu_dma_chan *dchan;
|
|
int i, ret;
|
|
|
|
hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
|
|
if (!hsu)
|
|
return;
|
|
|
|
/* Get basic io resource and map it */
|
|
hsu->paddr = 0xffa28000;
|
|
hsu->iolen = 0x1000;
|
|
|
|
if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
|
|
pr_warning("HSU: error in request mem region\n");
|
|
|
|
hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
|
|
if (!hsu->reg) {
|
|
pr_err("HSU: error in ioremap\n");
|
|
ret = -ENOMEM;
|
|
goto err_free_region;
|
|
}
|
|
|
|
/* Initialise the 3 UART ports */
|
|
uport = hsu->port;
|
|
for (i = 0; i < 3; i++) {
|
|
uport->port.type = PORT_MFD;
|
|
uport->port.iotype = UPIO_MEM;
|
|
uport->port.mapbase = (resource_size_t)hsu->paddr
|
|
+ HSU_PORT_REG_OFFSET
|
|
+ i * HSU_PORT_REG_LENGTH;
|
|
uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
|
|
+ i * HSU_PORT_REG_LENGTH;
|
|
|
|
sprintf(uport->name, "hsu_port%d", i);
|
|
uport->port.fifosize = 64;
|
|
uport->port.ops = &serial_hsu_pops;
|
|
uport->port.line = i;
|
|
uport->port.flags = UPF_IOREMAP;
|
|
/* set the scalable maxim support rate to 2746800 bps */
|
|
uport->port.uartclk = 115200 * 24 * 16;
|
|
|
|
uport->running = 0;
|
|
uport->txc = &hsu->chans[i * 2];
|
|
uport->rxc = &hsu->chans[i * 2 + 1];
|
|
|
|
serial_hsu_ports[i] = uport;
|
|
uport->index = i;
|
|
|
|
if (hsu_dma_enable & (1<<i))
|
|
uport->use_dma = 1;
|
|
else
|
|
uport->use_dma = 0;
|
|
|
|
uport++;
|
|
}
|
|
|
|
/* Initialise 6 dma channels */
|
|
dchan = hsu->chans;
|
|
for (i = 0; i < 6; i++) {
|
|
dchan->id = i;
|
|
dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
|
|
dchan->uport = &hsu->port[i/2];
|
|
dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
|
|
i * HSU_DMA_CHANS_REG_LENGTH;
|
|
|
|
dchan++;
|
|
}
|
|
|
|
phsu = hsu;
|
|
hsu_debugfs_init(hsu);
|
|
return;
|
|
|
|
err_free_region:
|
|
release_mem_region(hsu->paddr, hsu->iolen);
|
|
kfree(hsu);
|
|
return;
|
|
}
|
|
|
|
static void serial_hsu_remove(struct pci_dev *pdev)
|
|
{
|
|
void *priv = pci_get_drvdata(pdev);
|
|
struct uart_hsu_port *up;
|
|
|
|
if (!priv)
|
|
return;
|
|
|
|
pm_runtime_forbid(&pdev->dev);
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
|
|
/* For port 0/1/2, priv is the address of uart_hsu_port */
|
|
if (pdev->device != 0x081E) {
|
|
up = priv;
|
|
uart_remove_one_port(&serial_hsu_reg, &up->port);
|
|
}
|
|
|
|
pci_set_drvdata(pdev, NULL);
|
|
free_irq(pdev->irq, priv);
|
|
pci_disable_device(pdev);
|
|
}
|
|
|
|
/* First 3 are UART ports, and the 4th is the DMA */
|
|
static const struct pci_device_id pci_ids[] __devinitconst = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
|
|
{},
|
|
};
|
|
|
|
static struct pci_driver hsu_pci_driver = {
|
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.name = "HSU serial",
|
|
.id_table = pci_ids,
|
|
.probe = serial_hsu_probe,
|
|
.remove = __devexit_p(serial_hsu_remove),
|
|
.suspend = serial_hsu_suspend,
|
|
.resume = serial_hsu_resume,
|
|
.driver = {
|
|
.pm = &serial_hsu_pm_ops,
|
|
},
|
|
};
|
|
|
|
static int __init hsu_pci_init(void)
|
|
{
|
|
int ret;
|
|
|
|
hsu_global_init();
|
|
|
|
ret = uart_register_driver(&serial_hsu_reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return pci_register_driver(&hsu_pci_driver);
|
|
}
|
|
|
|
static void __exit hsu_pci_exit(void)
|
|
{
|
|
pci_unregister_driver(&hsu_pci_driver);
|
|
uart_unregister_driver(&serial_hsu_reg);
|
|
|
|
hsu_debugfs_remove(phsu);
|
|
|
|
kfree(phsu);
|
|
}
|
|
|
|
module_init(hsu_pci_init);
|
|
module_exit(hsu_pci_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:medfield-hsu");
|