0a88f4b557
The VIA family 6 model D CPU (C7-D, Eden 90 nm) can use two different VID tables, we have to check the value of a MSR to decide which one to use. Signed-off-by: Jean Delvare <khali@linux-fr.org> Acked-by: Guenter Roeck <guenter.roeck@ericsson.com> Tested-by: Jeff Rickman <jrickman@myamigos.us>
310 lines
9.8 KiB
C
310 lines
9.8 KiB
C
/*
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* hwmon-vid.c - VID/VRM/VRD voltage conversions
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*
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* Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz>
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*
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* Partly imported from i2c-vid.h of the lm_sensors project
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* Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
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* With assistance from Trent Piepho <xyzzy@speakeasy.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/hwmon-vid.h>
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/*
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* Common code for decoding VID pins.
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*
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* References:
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*
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* For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines",
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* available at http://developer.intel.com/.
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*
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* For VRD 10.0 and up, "VRD x.y Design Guide",
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* available at http://developer.intel.com/.
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*
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* AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
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* http://support.amd.com/us/Processor_TechDocs/26094.PDF
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* Table 74. VID Code Voltages
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* This corresponds to an arbitrary VRM code of 24 in the functions below.
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* These CPU models (K8 revision <= E) have 5 VID pins. See also:
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* Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
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*
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* AMD NPT Family 0Fh Processors, AMD Publication 32559,
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
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* Table 71. VID Code Voltages
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* This corresponds to an arbitrary VRM code of 25 in the functions below.
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* These CPU models (K8 revision >= F) have 6 VID pins. See also:
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* Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
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*
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* The 17 specification is in fact Intel Mobile Voltage Positioning -
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* (IMVP-II). You can find more information in the datasheet of Max1718
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* http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
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*
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* The 13 specification corresponds to the Intel Pentium M series. There
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* doesn't seem to be any named specification for these. The conversion
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* tables are detailed directly in the various Pentium M datasheets:
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* http://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm
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*
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* The 14 specification corresponds to Intel Core series. There
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* doesn't seem to be any named specification for these. The conversion
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* tables are detailed directly in the various Pentium Core datasheets:
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* http://www.intel.com/design/mobile/datashts/309221.htm
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*
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* The 110 (VRM 11) specification corresponds to Intel Conroe based series.
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* http://www.intel.com/design/processor/applnots/313214.htm
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*/
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/*
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* vrm is the VRM/VRD document version multiplied by 10.
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* val is the 4-bit or more VID code.
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* Returned value is in mV to avoid floating point in the kernel.
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* Some VID have some bits in uV scale, this is rounded to mV.
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*/
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int vid_from_reg(int val, u8 vrm)
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{
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int vid;
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switch(vrm) {
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case 100: /* VRD 10.0 */
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/* compute in uV, round to mV */
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val &= 0x3f;
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if((val & 0x1f) == 0x1f)
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return 0;
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if((val & 0x1f) <= 0x09 || val == 0x0a)
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vid = 1087500 - (val & 0x1f) * 25000;
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else
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vid = 1862500 - (val & 0x1f) * 25000;
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if(val & 0x20)
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vid -= 12500;
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return((vid + 500) / 1000);
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case 110: /* Intel Conroe */
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/* compute in uV, round to mV */
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val &= 0xff;
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if (val < 0x02 || val > 0xb2)
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return 0;
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return((1600000 - (val - 2) * 6250 + 500) / 1000);
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case 24: /* Athlon64 & Opteron */
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val &= 0x1f;
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if (val == 0x1f)
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return 0;
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/* fall through */
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case 25: /* AMD NPT 0Fh */
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val &= 0x3f;
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return (val < 32) ? 1550 - 25 * val
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: 775 - (25 * (val - 31)) / 2;
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case 91: /* VRM 9.1 */
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case 90: /* VRM 9.0 */
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val &= 0x1f;
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return(val == 0x1f ? 0 :
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1850 - val * 25);
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case 85: /* VRM 8.5 */
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val &= 0x1f;
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return((val & 0x10 ? 25 : 0) +
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((val & 0x0f) > 0x04 ? 2050 : 1250) -
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((val & 0x0f) * 50));
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case 84: /* VRM 8.4 */
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val &= 0x0f;
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/* fall through */
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case 82: /* VRM 8.2 */
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val &= 0x1f;
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return(val == 0x1f ? 0 :
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val & 0x10 ? 5100 - (val) * 100 :
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2050 - (val) * 50);
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case 17: /* Intel IMVP-II */
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val &= 0x1f;
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return(val & 0x10 ? 975 - (val & 0xF) * 25 :
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1750 - val * 50);
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case 13:
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case 131:
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val &= 0x3f;
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/* Exception for Eden ULV 500 MHz */
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if (vrm == 131 && val == 0x3f)
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val++;
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return(1708 - val * 16);
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case 14: /* Intel Core */
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/* compute in uV, round to mV */
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val &= 0x7f;
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return(val > 0x77 ? 0 : (1500000 - (val * 12500) + 500) / 1000);
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default: /* report 0 for unknown */
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if (vrm)
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pr_warn("Requested unsupported VRM version (%u)\n",
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(unsigned int)vrm);
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return 0;
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}
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}
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/*
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* After this point is the code to automatically determine which
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* VRM/VRD specification should be used depending on the CPU.
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*/
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struct vrm_model {
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u8 vendor;
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u8 eff_family;
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u8 eff_model;
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u8 eff_stepping;
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u8 vrm_type;
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};
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#define ANY 0xFF
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#ifdef CONFIG_X86
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/*
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* The stepping parameter is highest acceptable stepping for current line.
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* The model match must be exact for 4-bit values. For model values 0x10
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* and above (extended model), all models below the parameter will match.
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*/
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static struct vrm_model vrm_models[] = {
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{X86_VENDOR_AMD, 0x6, ANY, ANY, 90}, /* Athlon Duron etc */
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{X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24}, /* Athlon 64, Opteron */
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/* In theory, all NPT family 0Fh processors have 6 VID pins and should
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thus use vrm 25, however in practice not all mainboards route the
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6th VID pin because it is never needed. So we use the 5 VID pin
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variant (vrm 24) for the models which exist today. */
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{X86_VENDOR_AMD, 0xF, 0x7F, ANY, 24}, /* NPT family 0Fh */
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{X86_VENDOR_AMD, 0xF, ANY, ANY, 25}, /* future fam. 0Fh */
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{X86_VENDOR_AMD, 0x10, ANY, ANY, 25}, /* NPT family 10h */
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{X86_VENDOR_INTEL, 0x6, 0x9, ANY, 13}, /* Pentium M (130 nm) */
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{X86_VENDOR_INTEL, 0x6, 0xB, ANY, 85}, /* Tualatin */
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{X86_VENDOR_INTEL, 0x6, 0xD, ANY, 13}, /* Pentium M (90 nm) */
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{X86_VENDOR_INTEL, 0x6, 0xE, ANY, 14}, /* Intel Core (65 nm) */
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{X86_VENDOR_INTEL, 0x6, 0xF, ANY, 110}, /* Intel Conroe */
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{X86_VENDOR_INTEL, 0x6, ANY, ANY, 82}, /* any P6 */
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{X86_VENDOR_INTEL, 0xF, 0x0, ANY, 90}, /* P4 */
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{X86_VENDOR_INTEL, 0xF, 0x1, ANY, 90}, /* P4 Willamette */
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{X86_VENDOR_INTEL, 0xF, 0x2, ANY, 90}, /* P4 Northwood */
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{X86_VENDOR_INTEL, 0xF, ANY, ANY, 100}, /* Prescott and above assume VRD 10 */
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{X86_VENDOR_CENTAUR, 0x6, 0x7, ANY, 85}, /* Eden ESP/Ezra */
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{X86_VENDOR_CENTAUR, 0x6, 0x8, 0x7, 85}, /* Ezra T */
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{X86_VENDOR_CENTAUR, 0x6, 0x9, 0x7, 85}, /* Nehemiah */
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{X86_VENDOR_CENTAUR, 0x6, 0x9, ANY, 17}, /* C3-M, Eden-N */
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{X86_VENDOR_CENTAUR, 0x6, 0xA, 0x7, 0}, /* No information */
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{X86_VENDOR_CENTAUR, 0x6, 0xA, ANY, 13}, /* C7-M, C7, Eden (Esther) */
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{X86_VENDOR_CENTAUR, 0x6, 0xD, ANY, 134}, /* C7-D, C7-M, C7, Eden (Esther) */
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{X86_VENDOR_UNKNOWN, ANY, ANY, ANY, 0} /* stop here */
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};
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/*
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* Special case for VIA model D: there are two different possible
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* VID tables, so we have to figure out first, which one must be
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* used. This resolves temporary drm value 134 to 14 (Intel Core
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* 7-bit VID), 13 (Pentium M 6-bit VID) or 131 (Pentium M 6-bit VID
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* + quirk for Eden ULV 500 MHz).
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* Note: something similar might be needed for model A, I'm not sure.
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*/
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static u8 get_via_model_d_vrm(void)
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{
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unsigned int vid, brand, dummy;
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static const char *brands[4] = {
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"C7-M", "C7", "Eden", "C7-D"
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};
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rdmsr(0x198, dummy, vid);
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vid &= 0xff;
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rdmsr(0x1154, brand, dummy);
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brand = ((brand >> 4) ^ (brand >> 2)) & 0x03;
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if (vid > 0x3f) {
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pr_info("Using %d-bit VID table for VIA %s CPU\n",
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7, brands[brand]);
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return 14;
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} else {
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pr_info("Using %d-bit VID table for VIA %s CPU\n",
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6, brands[brand]);
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/* Enable quirk for Eden */
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return brand == 2 ? 131 : 13;
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}
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}
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static u8 find_vrm(u8 eff_family, u8 eff_model, u8 eff_stepping, u8 vendor)
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{
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int i = 0;
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while (vrm_models[i].vendor!=X86_VENDOR_UNKNOWN) {
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if (vrm_models[i].vendor==vendor)
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if ((vrm_models[i].eff_family==eff_family)
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&& ((vrm_models[i].eff_model==eff_model) ||
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(vrm_models[i].eff_model >= 0x10 &&
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eff_model <= vrm_models[i].eff_model) ||
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(vrm_models[i].eff_model==ANY)) &&
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(eff_stepping <= vrm_models[i].eff_stepping))
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return vrm_models[i].vrm_type;
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i++;
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}
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return 0;
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}
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u8 vid_which_vrm(void)
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{
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struct cpuinfo_x86 *c = &cpu_data(0);
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u32 eax;
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u8 eff_family, eff_model, eff_stepping, vrm_ret;
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if (c->x86 < 6) /* Any CPU with family lower than 6 */
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return 0; /* doesn't have VID and/or CPUID */
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eax = cpuid_eax(1);
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eff_family = ((eax & 0x00000F00)>>8);
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eff_model = ((eax & 0x000000F0)>>4);
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eff_stepping = eax & 0xF;
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if (eff_family == 0xF) { /* use extended model & family */
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eff_family += ((eax & 0x00F00000)>>20);
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eff_model += ((eax & 0x000F0000)>>16)<<4;
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}
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vrm_ret = find_vrm(eff_family, eff_model, eff_stepping, c->x86_vendor);
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if (vrm_ret == 134)
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vrm_ret = get_via_model_d_vrm();
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if (vrm_ret == 0)
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pr_info("Unknown VRM version of your x86 CPU\n");
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return vrm_ret;
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}
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/* and now for something completely different for the non-x86 world */
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#else
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u8 vid_which_vrm(void)
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{
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pr_info("Unknown VRM version of your CPU\n");
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return 0;
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}
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#endif
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EXPORT_SYMBOL(vid_from_reg);
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EXPORT_SYMBOL(vid_which_vrm);
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MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
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MODULE_DESCRIPTION("hwmon-vid driver");
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MODULE_LICENSE("GPL");
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