 6f61415e9c
			
		
	
	
	6f61415e9c
	
	
	
		
			
			Where appropriate factor out some boilerplate code for platform device registration into module_platform_driver. Drivers that don't use the standard module_init initcall haven't been converted. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
		
			
				
	
	
		
			305 lines
		
	
	
	
		
			6.5 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			305 lines
		
	
	
	
		
			6.5 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * GPIO interface for Intel Poulsbo SCH
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|  *
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|  *  Copyright (c) 2010 CompuLab Ltd
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|  *  Author: Denis Turischev <denis@compulab.co.il>
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|  *
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|  *  This program is free software; you can redistribute it and/or modify
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|  *  it under the terms of the GNU General Public License 2 as published
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|  *  by the Free Software Foundation.
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|  *
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|  *  This program is distributed in the hope that it will be useful,
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|  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  *  GNU General Public License for more details.
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|  *
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|  *  You should have received a copy of the GNU General Public License
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|  *  along with this program; see the file COPYING.  If not, write to
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|  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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|  */
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| 
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| #include <linux/init.h>
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| #include <linux/kernel.h>
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| #include <linux/module.h>
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| #include <linux/io.h>
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| #include <linux/errno.h>
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| #include <linux/acpi.h>
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| #include <linux/platform_device.h>
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| #include <linux/pci_ids.h>
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| 
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| #include <linux/gpio.h>
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| 
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| static DEFINE_SPINLOCK(gpio_lock);
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| 
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| #define CGEN	(0x00)
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| #define CGIO	(0x04)
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| #define CGLV	(0x08)
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| 
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| #define RGEN	(0x20)
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| #define RGIO	(0x24)
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| #define RGLV	(0x28)
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| 
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| static unsigned short gpio_ba;
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| 
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| static int sch_gpio_core_direction_in(struct gpio_chip *gc, unsigned  gpio_num)
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| {
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| 	u8 curr_dirs;
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| 	unsigned short offset, bit;
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| 
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| 	spin_lock(&gpio_lock);
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| 
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| 	offset = CGIO + gpio_num / 8;
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| 	bit = gpio_num % 8;
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| 
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| 	curr_dirs = inb(gpio_ba + offset);
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| 
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| 	if (!(curr_dirs & (1 << bit)))
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| 		outb(curr_dirs | (1 << bit), gpio_ba + offset);
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| 
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| 	spin_unlock(&gpio_lock);
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| 	return 0;
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| }
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| 
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| static int sch_gpio_core_get(struct gpio_chip *gc, unsigned gpio_num)
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| {
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| 	int res;
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| 	unsigned short offset, bit;
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| 
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| 	offset = CGLV + gpio_num / 8;
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| 	bit = gpio_num % 8;
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| 
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| 	res = !!(inb(gpio_ba + offset) & (1 << bit));
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| 	return res;
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| }
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| 
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| static void sch_gpio_core_set(struct gpio_chip *gc, unsigned gpio_num, int val)
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| {
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| 	u8 curr_vals;
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| 	unsigned short offset, bit;
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| 
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| 	spin_lock(&gpio_lock);
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| 
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| 	offset = CGLV + gpio_num / 8;
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| 	bit = gpio_num % 8;
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| 
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| 	curr_vals = inb(gpio_ba + offset);
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| 
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| 	if (val)
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| 		outb(curr_vals | (1 << bit), gpio_ba + offset);
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| 	else
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| 		outb((curr_vals & ~(1 << bit)), gpio_ba + offset);
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| 	spin_unlock(&gpio_lock);
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| }
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| 
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| static int sch_gpio_core_direction_out(struct gpio_chip *gc,
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| 					unsigned gpio_num, int val)
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| {
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| 	u8 curr_dirs;
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| 	unsigned short offset, bit;
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| 
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| 	sch_gpio_core_set(gc, gpio_num, val);
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| 
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| 	spin_lock(&gpio_lock);
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| 
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| 	offset = CGIO + gpio_num / 8;
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| 	bit = gpio_num % 8;
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| 
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| 	curr_dirs = inb(gpio_ba + offset);
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| 	if (curr_dirs & (1 << bit))
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| 		outb(curr_dirs & ~(1 << bit), gpio_ba + offset);
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| 
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| 	spin_unlock(&gpio_lock);
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| 	return 0;
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| }
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| 
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| static struct gpio_chip sch_gpio_core = {
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| 	.label			= "sch_gpio_core",
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| 	.owner			= THIS_MODULE,
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| 	.direction_input	= sch_gpio_core_direction_in,
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| 	.get			= sch_gpio_core_get,
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| 	.direction_output	= sch_gpio_core_direction_out,
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| 	.set			= sch_gpio_core_set,
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| };
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| 
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| static int sch_gpio_resume_direction_in(struct gpio_chip *gc,
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| 					unsigned gpio_num)
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| {
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| 	u8 curr_dirs;
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| 
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| 	spin_lock(&gpio_lock);
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| 
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| 	curr_dirs = inb(gpio_ba + RGIO);
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| 
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| 	if (!(curr_dirs & (1 << gpio_num)))
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| 		outb(curr_dirs | (1 << gpio_num) , gpio_ba + RGIO);
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| 
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| 	spin_unlock(&gpio_lock);
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| 	return 0;
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| }
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| 
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| static int sch_gpio_resume_get(struct gpio_chip *gc, unsigned gpio_num)
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| {
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| 	return !!(inb(gpio_ba + RGLV) & (1 << gpio_num));
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| }
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| 
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| static void sch_gpio_resume_set(struct gpio_chip *gc,
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| 				unsigned gpio_num, int val)
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| {
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| 	u8 curr_vals;
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| 
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| 	spin_lock(&gpio_lock);
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| 
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| 	curr_vals = inb(gpio_ba + RGLV);
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| 
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| 	if (val)
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| 		outb(curr_vals | (1 << gpio_num), gpio_ba + RGLV);
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| 	else
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| 		outb((curr_vals & ~(1 << gpio_num)), gpio_ba + RGLV);
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| 
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| 	spin_unlock(&gpio_lock);
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| }
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| 
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| static int sch_gpio_resume_direction_out(struct gpio_chip *gc,
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| 					unsigned gpio_num, int val)
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| {
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| 	u8 curr_dirs;
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| 
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| 	sch_gpio_resume_set(gc, gpio_num, val);
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| 
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| 	spin_lock(&gpio_lock);
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| 
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| 	curr_dirs = inb(gpio_ba + RGIO);
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| 	if (curr_dirs & (1 << gpio_num))
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| 		outb(curr_dirs & ~(1 << gpio_num), gpio_ba + RGIO);
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| 
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| 	spin_unlock(&gpio_lock);
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| 	return 0;
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| }
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| 
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| static struct gpio_chip sch_gpio_resume = {
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| 	.label			= "sch_gpio_resume",
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| 	.owner			= THIS_MODULE,
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| 	.direction_input	= sch_gpio_resume_direction_in,
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| 	.get			= sch_gpio_resume_get,
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| 	.direction_output	= sch_gpio_resume_direction_out,
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| 	.set			= sch_gpio_resume_set,
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| };
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| 
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| static int __devinit sch_gpio_probe(struct platform_device *pdev)
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| {
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| 	struct resource *res;
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| 	int err, id;
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| 
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| 	id = pdev->id;
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| 	if (!id)
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| 		return -ENODEV;
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| 
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| 	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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| 	if (!res)
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| 		return -EBUSY;
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| 
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| 	if (!request_region(res->start, resource_size(res), pdev->name))
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| 		return -EBUSY;
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| 
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| 	gpio_ba = res->start;
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| 
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| 	switch (id) {
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| 		case PCI_DEVICE_ID_INTEL_SCH_LPC:
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| 			sch_gpio_core.base = 0;
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| 			sch_gpio_core.ngpio = 10;
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| 
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| 			sch_gpio_resume.base = 10;
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| 			sch_gpio_resume.ngpio = 4;
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| 
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| 			/*
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| 			 * GPIO[6:0] enabled by default
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| 			 * GPIO7 is configured by the CMC as SLPIOVR
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| 			 * Enable GPIO[9:8] core powered gpios explicitly
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| 			 */
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| 			outb(0x3, gpio_ba + CGEN + 1);
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| 			/*
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| 			 * SUS_GPIO[2:0] enabled by default
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| 			 * Enable SUS_GPIO3 resume powered gpio explicitly
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| 			 */
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| 			outb(0x8, gpio_ba + RGEN);
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| 			break;
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| 
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| 		case PCI_DEVICE_ID_INTEL_ITC_LPC:
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| 			sch_gpio_core.base = 0;
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| 			sch_gpio_core.ngpio = 5;
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| 
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| 			sch_gpio_resume.base = 5;
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| 			sch_gpio_resume.ngpio = 9;
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| 			break;
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| 
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| 		default:
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| 			return -ENODEV;
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| 	}
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| 
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| 	sch_gpio_core.dev = &pdev->dev;
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| 	sch_gpio_resume.dev = &pdev->dev;
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| 
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| 	err = gpiochip_add(&sch_gpio_core);
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| 	if (err < 0)
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| 		goto err_sch_gpio_core;
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| 
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| 	err = gpiochip_add(&sch_gpio_resume);
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| 	if (err < 0)
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| 		goto err_sch_gpio_resume;
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| 
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| 	return 0;
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| 
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| err_sch_gpio_resume:
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| 	err = gpiochip_remove(&sch_gpio_core);
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| 	if (err)
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| 		dev_err(&pdev->dev, "%s failed, %d\n",
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| 				"gpiochip_remove()", err);
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| 
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| err_sch_gpio_core:
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| 	release_region(res->start, resource_size(res));
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| 	gpio_ba = 0;
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| 
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| 	return err;
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| }
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| 
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| static int __devexit sch_gpio_remove(struct platform_device *pdev)
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| {
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| 	struct resource *res;
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| 	if (gpio_ba) {
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| 		int err;
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| 
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| 		err  = gpiochip_remove(&sch_gpio_core);
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| 		if (err)
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| 			dev_err(&pdev->dev, "%s failed, %d\n",
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| 				"gpiochip_remove()", err);
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| 		err = gpiochip_remove(&sch_gpio_resume);
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| 		if (err)
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| 			dev_err(&pdev->dev, "%s failed, %d\n",
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| 				"gpiochip_remove()", err);
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| 
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| 		res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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| 
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| 		release_region(res->start, resource_size(res));
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| 		gpio_ba = 0;
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| 
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| 		return err;
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| static struct platform_driver sch_gpio_driver = {
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| 	.driver = {
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| 		.name = "sch_gpio",
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| 		.owner = THIS_MODULE,
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| 	},
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| 	.probe		= sch_gpio_probe,
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| 	.remove		= __devexit_p(sch_gpio_remove),
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| };
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| 
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| module_platform_driver(sch_gpio_driver);
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| 
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| MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
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| MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
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| MODULE_LICENSE("GPL");
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| MODULE_ALIAS("platform:sch_gpio");
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