daea1175a9
This adds a udbg and an hvc console backend for supporting a console using the OPAL console interfaces. On OPAL v1 we have hvc0 mapped to whatever console the system was configured for (network or hvsi serial port) via the service processor. On OPAL v2 we have hvcN mapped to the Nth console provided by OPAL which generally corresponds to: hvc0 : network console (raw protocol) hvc1 : serial port S1 (hvsi) hvc2 : serial port S2 (hvsi) Note: At this point, early debug console only works with OPAL v1 and shouldn't be enabled in a normal kernel. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
809 lines
20 KiB
ArmAsm
809 lines
20 KiB
ArmAsm
/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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*
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* Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
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* Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
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*
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* This file contains the entry point for the 64-bit kernel along
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* with some early initialization code common to all 64-bit powerpc
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* variants.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/bug.h>
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#include <asm/cputable.h>
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#include <asm/setup.h>
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#include <asm/hvcall.h>
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#include <asm/iseries/lpar_map.h>
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#include <asm/thread_info.h>
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#include <asm/firmware.h>
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#include <asm/page_64.h>
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#include <asm/irqflags.h>
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#include <asm/kvm_book3s_asm.h>
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#include <asm/ptrace.h>
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/* The physical memory is laid out such that the secondary processor
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* spin code sits at 0x0000...0x00ff. On server, the vectors follow
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* using the layout described in exceptions-64s.S
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*/
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/*
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* Entering into this code we make the following assumptions:
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*
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* For pSeries or server processors:
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* 1. The MMU is off & open firmware is running in real mode.
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* 2. The kernel is entered at __start
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* -or- For OPAL entry:
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* 1. The MMU is off, processor in HV mode, primary CPU enters at 0
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* with device-tree in gpr3. We also get OPAL base in r8 and
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* entry in r9 for debugging purposes
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* 2. Secondary processors enter at 0x60 with PIR in gpr3
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*
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* For iSeries:
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* 1. The MMU is on (as it always is for iSeries)
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* 2. The kernel is entered at system_reset_iSeries
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*
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* For Book3E processors:
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* 1. The MMU is on running in AS0 in a state defined in ePAPR
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* 2. The kernel is entered at __start
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*/
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.text
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.globl _stext
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_stext:
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_GLOBAL(__start)
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/* NOP this out unconditionally */
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BEGIN_FTR_SECTION
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b .__start_initialization_multiplatform
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END_FTR_SECTION(0, 1)
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/* Catch branch to 0 in real mode */
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trap
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/* Secondary processors spin on this value until it becomes nonzero.
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* When it does it contains the real address of the descriptor
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* of the function that the cpu should jump to to continue
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* initialization.
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*/
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.globl __secondary_hold_spinloop
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__secondary_hold_spinloop:
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.llong 0x0
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/* Secondary processors write this value with their cpu # */
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/* after they enter the spin loop immediately below. */
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.globl __secondary_hold_acknowledge
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__secondary_hold_acknowledge:
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.llong 0x0
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#ifdef CONFIG_PPC_ISERIES
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/*
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* At offset 0x20, there is a pointer to iSeries LPAR data.
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* This is required by the hypervisor
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*/
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. = 0x20
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.llong hvReleaseData-KERNELBASE
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#endif /* CONFIG_PPC_ISERIES */
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#ifdef CONFIG_RELOCATABLE
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/* This flag is set to 1 by a loader if the kernel should run
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* at the loaded address instead of the linked address. This
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* is used by kexec-tools to keep the the kdump kernel in the
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* crash_kernel region. The loader is responsible for
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* observing the alignment requirement.
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*/
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/* Do not move this variable as kexec-tools knows about it. */
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. = 0x5c
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.globl __run_at_load
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__run_at_load:
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.long 0x72756e30 /* "run0" -- relocate to 0 by default */
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#endif
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. = 0x60
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/*
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* The following code is used to hold secondary processors
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* in a spin loop after they have entered the kernel, but
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* before the bulk of the kernel has been relocated. This code
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* is relocated to physical address 0x60 before prom_init is run.
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* All of it must fit below the first exception vector at 0x100.
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* Use .globl here not _GLOBAL because we want __secondary_hold
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* to be the actual text address, not a descriptor.
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*/
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.globl __secondary_hold
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__secondary_hold:
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#ifndef CONFIG_PPC_BOOK3E
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mfmsr r24
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ori r24,r24,MSR_RI
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mtmsrd r24 /* RI on */
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#endif
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/* Grab our physical cpu number */
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mr r24,r3
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/* Tell the master cpu we're here */
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/* Relocation is off & we are located at an address less */
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/* than 0x100, so only need to grab low order offset. */
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std r24,__secondary_hold_acknowledge-_stext(0)
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sync
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/* All secondary cpus wait here until told to start. */
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100: ld r4,__secondary_hold_spinloop-_stext(0)
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cmpdi 0,r4,0
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beq 100b
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#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
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ld r4,0(r4) /* deref function descriptor */
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mtctr r4
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mr r3,r24
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li r4,0
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/* Make sure that patched code is visible */
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isync
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bctr
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#else
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BUG_OPCODE
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#endif
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/* This value is used to mark exception frames on the stack. */
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.section ".toc","aw"
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exception_marker:
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.tc ID_72656773_68657265[TC],0x7265677368657265
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.text
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/*
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* On server, we include the exception vectors code here as it
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* relies on absolute addressing which is only possible within
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* this compilation unit
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*/
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#ifdef CONFIG_PPC_BOOK3S
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#include "exceptions-64s.S"
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#endif
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_GLOBAL(generic_secondary_thread_init)
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mr r24,r3
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/* turn on 64-bit mode */
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bl .enable_64b_mode
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/* get a valid TOC pointer, wherever we're mapped at */
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bl .relative_toc
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#ifdef CONFIG_PPC_BOOK3E
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/* Book3E initialization */
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mr r3,r24
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bl .book3e_secondary_thread_init
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#endif
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b generic_secondary_common_init
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/*
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* On pSeries and most other platforms, secondary processors spin
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* in the following code.
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* At entry, r3 = this processor's number (physical cpu id)
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*
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* On Book3E, r4 = 1 to indicate that the initial TLB entry for
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* this core already exists (setup via some other mechanism such
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* as SCOM before entry).
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*/
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_GLOBAL(generic_secondary_smp_init)
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mr r24,r3
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mr r25,r4
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/* turn on 64-bit mode */
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bl .enable_64b_mode
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/* get a valid TOC pointer, wherever we're mapped at */
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bl .relative_toc
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#ifdef CONFIG_PPC_BOOK3E
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/* Book3E initialization */
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mr r3,r24
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mr r4,r25
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bl .book3e_secondary_core_init
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#endif
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generic_secondary_common_init:
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/* Set up a paca value for this processor. Since we have the
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* physical cpu id in r24, we need to search the pacas to find
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* which logical id maps to our physical one.
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*/
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LOAD_REG_ADDR(r13, paca) /* Load paca pointer */
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ld r13,0(r13) /* Get base vaddr of paca array */
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#ifndef CONFIG_SMP
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addi r13,r13,PACA_SIZE /* know r13 if used accidentally */
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b .kexec_wait /* wait for next kernel if !SMP */
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#else
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LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
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lwz r7,0(r7) /* also the max paca allocated */
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li r5,0 /* logical cpu id */
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1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
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cmpw r6,r24 /* Compare to our id */
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beq 2f
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addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
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addi r5,r5,1
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cmpw r5,r7 /* Check if more pacas exist */
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blt 1b
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mr r3,r24 /* not found, copy phys to r3 */
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b .kexec_wait /* next kernel might do better */
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2: SET_PACA(r13)
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#ifdef CONFIG_PPC_BOOK3E
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addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
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mtspr SPRN_SPRG_TLB_EXFRAME,r12
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#endif
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/* From now on, r24 is expected to be logical cpuid */
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mr r24,r5
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/* See if we need to call a cpu state restore handler */
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LOAD_REG_ADDR(r23, cur_cpu_spec)
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ld r23,0(r23)
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ld r23,CPU_SPEC_RESTORE(r23)
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cmpdi 0,r23,0
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beq 3f
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ld r23,0(r23)
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mtctr r23
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bctrl
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3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
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lwarx r4,0,r3
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subi r4,r4,1
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stwcx. r4,0,r3
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bne 3b
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isync
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4: HMT_LOW
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lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
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/* start. */
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cmpwi 0,r23,0
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beq 4b /* Loop until told to go */
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sync /* order paca.run and cur_cpu_spec */
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isync /* In case code patching happened */
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/* Create a temp kernel stack for use before relocation is on. */
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ld r1,PACAEMERGSP(r13)
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subi r1,r1,STACK_FRAME_OVERHEAD
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b __secondary_start
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#endif /* SMP */
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/*
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* Turn the MMU off.
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* Assumes we're mapped EA == RA if the MMU is on.
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*/
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#ifdef CONFIG_PPC_BOOK3S
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_STATIC(__mmu_off)
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mfmsr r3
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andi. r0,r3,MSR_IR|MSR_DR
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beqlr
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mflr r4
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andc r3,r3,r0
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mtspr SPRN_SRR0,r4
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mtspr SPRN_SRR1,r3
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sync
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rfid
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b . /* prevent speculative execution */
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#endif
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/*
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* Here is our main kernel entry point. We support currently 2 kind of entries
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* depending on the value of r5.
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*
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* r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
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* in r3...r7
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*
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* r5 == NULL -> kexec style entry. r3 is a physical pointer to the
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* DT block, r4 is a physical pointer to the kernel itself
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*
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*/
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_GLOBAL(__start_initialization_multiplatform)
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/* Make sure we are running in 64 bits mode */
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bl .enable_64b_mode
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/* Get TOC pointer (current runtime address) */
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bl .relative_toc
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/* find out where we are now */
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bcl 20,31,$+4
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0: mflr r26 /* r26 = runtime addr here */
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addis r26,r26,(_stext - 0b)@ha
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addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
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/*
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* Are we booted from a PROM Of-type client-interface ?
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*/
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cmpldi cr0,r5,0
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beq 1f
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b .__boot_from_prom /* yes -> prom */
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1:
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/* Save parameters */
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mr r31,r3
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mr r30,r4
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#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
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/* Save OPAL entry */
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mr r28,r8
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mr r29,r9
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#endif
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#ifdef CONFIG_PPC_BOOK3E
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bl .start_initialization_book3e
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b .__after_prom_start
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#else
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/* Setup some critical 970 SPRs before switching MMU off */
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mfspr r0,SPRN_PVR
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srwi r0,r0,16
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cmpwi r0,0x39 /* 970 */
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beq 1f
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cmpwi r0,0x3c /* 970FX */
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beq 1f
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cmpwi r0,0x44 /* 970MP */
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beq 1f
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cmpwi r0,0x45 /* 970GX */
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bne 2f
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1: bl .__cpu_preinit_ppc970
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2:
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/* Switch off MMU if not already off */
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bl .__mmu_off
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b .__after_prom_start
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#endif /* CONFIG_PPC_BOOK3E */
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_INIT_STATIC(__boot_from_prom)
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#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
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/* Save parameters */
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mr r31,r3
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mr r30,r4
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mr r29,r5
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mr r28,r6
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mr r27,r7
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/*
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* Align the stack to 16-byte boundary
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* Depending on the size and layout of the ELF sections in the initial
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* boot binary, the stack pointer may be unaligned on PowerMac
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*/
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rldicr r1,r1,0,59
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#ifdef CONFIG_RELOCATABLE
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/* Relocate code for where we are now */
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mr r3,r26
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bl .relocate
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#endif
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/* Restore parameters */
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mr r3,r31
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mr r4,r30
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mr r5,r29
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mr r6,r28
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mr r7,r27
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/* Do all of the interaction with OF client interface */
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mr r8,r26
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bl .prom_init
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#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
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/* We never return. We also hit that trap if trying to boot
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* from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
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trap
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_STATIC(__after_prom_start)
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#ifdef CONFIG_RELOCATABLE
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/* process relocations for the final address of the kernel */
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lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
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sldi r25,r25,32
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lwz r7,__run_at_load-_stext(r26)
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cmplwi cr0,r7,1 /* flagged to stay where we are ? */
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bne 1f
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add r25,r25,r26
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1: mr r3,r25
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bl .relocate
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#endif
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/*
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* We need to run with _stext at physical address PHYSICAL_START.
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* This will leave some code in the first 256B of
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* real memory, which are reserved for software use.
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*
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* Note: This process overwrites the OF exception vectors.
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*/
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li r3,0 /* target addr */
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#ifdef CONFIG_PPC_BOOK3E
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tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
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#endif
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mr. r4,r26 /* In some cases the loader may */
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beq 9f /* have already put us at zero */
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li r6,0x100 /* Start offset, the first 0x100 */
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/* bytes were copied earlier. */
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#ifdef CONFIG_PPC_BOOK3E
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tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */
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#endif
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#ifdef CONFIG_CRASH_DUMP
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/*
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* Check if the kernel has to be running as relocatable kernel based on the
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* variable __run_at_load, if it is set the kernel is treated as relocatable
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* kernel, otherwise it will be moved to PHYSICAL_START
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*/
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lwz r7,__run_at_load-_stext(r26)
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cmplwi cr0,r7,1
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bne 3f
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li r5,__end_interrupts - _stext /* just copy interrupts */
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b 5f
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3:
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#endif
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lis r5,(copy_to_here - _stext)@ha
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addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */
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bl .copy_and_flush /* copy the first n bytes */
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/* this includes the code being */
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/* executed here. */
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addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */
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addi r8,r8,(4f - _stext)@l /* that we just made */
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mtctr r8
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bctr
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p_end: .llong _end - _stext
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4: /* Now copy the rest of the kernel up to _end */
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addis r5,r26,(p_end - _stext)@ha
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ld r5,(p_end - _stext)@l(r5) /* get _end */
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5: bl .copy_and_flush /* copy the rest */
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9: b .start_here_multiplatform
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/*
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* Copy routine used to copy the kernel to start at physical address 0
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* and flush and invalidate the caches as needed.
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* r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
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* on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
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*
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* Note: this routine *only* clobbers r0, r6 and lr
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*/
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_GLOBAL(copy_and_flush)
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addi r5,r5,-8
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addi r6,r6,-8
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4: li r0,8 /* Use the smallest common */
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/* denominator cache line */
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/* size. This results in */
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/* extra cache line flushes */
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/* but operation is correct. */
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/* Can't get cache line size */
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/* from NACA as it is being */
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/* moved too. */
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mtctr r0 /* put # words/line in ctr */
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3: addi r6,r6,8 /* copy a cache line */
|
|
ldx r0,r6,r4
|
|
stdx r0,r6,r3
|
|
bdnz 3b
|
|
dcbst r6,r3 /* write it to memory */
|
|
sync
|
|
icbi r6,r3 /* flush the icache line */
|
|
cmpld 0,r6,r5
|
|
blt 4b
|
|
sync
|
|
addi r5,r5,8
|
|
addi r6,r6,8
|
|
blr
|
|
|
|
.align 8
|
|
copy_to_here:
|
|
|
|
#ifdef CONFIG_SMP
|
|
#ifdef CONFIG_PPC_PMAC
|
|
/*
|
|
* On PowerMac, secondary processors starts from the reset vector, which
|
|
* is temporarily turned into a call to one of the functions below.
|
|
*/
|
|
.section ".text";
|
|
.align 2 ;
|
|
|
|
.globl __secondary_start_pmac_0
|
|
__secondary_start_pmac_0:
|
|
/* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
|
|
li r24,0
|
|
b 1f
|
|
li r24,1
|
|
b 1f
|
|
li r24,2
|
|
b 1f
|
|
li r24,3
|
|
1:
|
|
|
|
_GLOBAL(pmac_secondary_start)
|
|
/* turn on 64-bit mode */
|
|
bl .enable_64b_mode
|
|
|
|
li r0,0
|
|
mfspr r3,SPRN_HID4
|
|
rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
|
|
sync
|
|
mtspr SPRN_HID4,r3
|
|
isync
|
|
sync
|
|
slbia
|
|
|
|
/* get TOC pointer (real address) */
|
|
bl .relative_toc
|
|
|
|
/* Copy some CPU settings from CPU 0 */
|
|
bl .__restore_cpu_ppc970
|
|
|
|
/* pSeries do that early though I don't think we really need it */
|
|
mfmsr r3
|
|
ori r3,r3,MSR_RI
|
|
mtmsrd r3 /* RI on */
|
|
|
|
/* Set up a paca value for this processor. */
|
|
LOAD_REG_ADDR(r4,paca) /* Load paca pointer */
|
|
ld r4,0(r4) /* Get base vaddr of paca array */
|
|
mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
|
|
add r13,r13,r4 /* for this processor. */
|
|
SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
|
|
|
|
/* Mark interrupts soft and hard disabled (they might be enabled
|
|
* in the PACA when doing hotplug)
|
|
*/
|
|
li r0,0
|
|
stb r0,PACASOFTIRQEN(r13)
|
|
stb r0,PACAHARDIRQEN(r13)
|
|
|
|
/* Create a temp kernel stack for use before relocation is on. */
|
|
ld r1,PACAEMERGSP(r13)
|
|
subi r1,r1,STACK_FRAME_OVERHEAD
|
|
|
|
b __secondary_start
|
|
|
|
#endif /* CONFIG_PPC_PMAC */
|
|
|
|
/*
|
|
* This function is called after the master CPU has released the
|
|
* secondary processors. The execution environment is relocation off.
|
|
* The paca for this processor has the following fields initialized at
|
|
* this point:
|
|
* 1. Processor number
|
|
* 2. Segment table pointer (virtual address)
|
|
* On entry the following are set:
|
|
* r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
|
|
* r24 = cpu# (in Linux terms)
|
|
* r13 = paca virtual address
|
|
* SPRG_PACA = paca virtual address
|
|
*/
|
|
.section ".text";
|
|
.align 2 ;
|
|
|
|
.globl __secondary_start
|
|
__secondary_start:
|
|
/* Set thread priority to MEDIUM */
|
|
HMT_MEDIUM
|
|
|
|
/* Initialize the kernel stack. Just a repeat for iSeries. */
|
|
LOAD_REG_ADDR(r3, current_set)
|
|
sldi r28,r24,3 /* get current_set[cpu#] */
|
|
ldx r14,r3,r28
|
|
addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD
|
|
std r14,PACAKSAVE(r13)
|
|
|
|
/* Do early setup for that CPU (stab, slb, hash table pointer) */
|
|
bl .early_setup_secondary
|
|
|
|
/*
|
|
* setup the new stack pointer, but *don't* use this until
|
|
* translation is on.
|
|
*/
|
|
mr r1, r14
|
|
|
|
/* Clear backchain so we get nice backtraces */
|
|
li r7,0
|
|
mtlr r7
|
|
|
|
/* enable MMU and jump to start_secondary */
|
|
LOAD_REG_ADDR(r3, .start_secondary_prolog)
|
|
LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
|
|
#ifdef CONFIG_PPC_ISERIES
|
|
BEGIN_FW_FTR_SECTION
|
|
ori r4,r4,MSR_EE
|
|
li r8,1
|
|
stb r8,PACAHARDIRQEN(r13)
|
|
END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
|
|
#endif
|
|
BEGIN_FW_FTR_SECTION
|
|
stb r7,PACAHARDIRQEN(r13)
|
|
END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
|
|
stb r7,PACASOFTIRQEN(r13)
|
|
|
|
mtspr SPRN_SRR0,r3
|
|
mtspr SPRN_SRR1,r4
|
|
RFI
|
|
b . /* prevent speculative execution */
|
|
|
|
/*
|
|
* Running with relocation on at this point. All we want to do is
|
|
* zero the stack back-chain pointer and get the TOC virtual address
|
|
* before going into C code.
|
|
*/
|
|
_GLOBAL(start_secondary_prolog)
|
|
ld r2,PACATOC(r13)
|
|
li r3,0
|
|
std r3,0(r1) /* Zero the stack frame pointer */
|
|
bl .start_secondary
|
|
b .
|
|
/*
|
|
* Reset stack pointer and call start_secondary
|
|
* to continue with online operation when woken up
|
|
* from cede in cpu offline.
|
|
*/
|
|
_GLOBAL(start_secondary_resume)
|
|
ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
|
|
li r3,0
|
|
std r3,0(r1) /* Zero the stack frame pointer */
|
|
bl .start_secondary
|
|
b .
|
|
#endif
|
|
|
|
/*
|
|
* This subroutine clobbers r11 and r12
|
|
*/
|
|
_GLOBAL(enable_64b_mode)
|
|
mfmsr r11 /* grab the current MSR */
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
|
|
mtmsr r11
|
|
#else /* CONFIG_PPC_BOOK3E */
|
|
li r12,(MSR_64BIT | MSR_ISF)@highest
|
|
sldi r12,r12,48
|
|
or r11,r11,r12
|
|
mtmsrd r11
|
|
isync
|
|
#endif
|
|
blr
|
|
|
|
/*
|
|
* This puts the TOC pointer into r2, offset by 0x8000 (as expected
|
|
* by the toolchain). It computes the correct value for wherever we
|
|
* are running at the moment, using position-independent code.
|
|
*/
|
|
_GLOBAL(relative_toc)
|
|
mflr r0
|
|
bcl 20,31,$+4
|
|
0: mflr r11
|
|
ld r2,(p_toc - 0b)(r11)
|
|
add r2,r2,r11
|
|
mtlr r0
|
|
blr
|
|
|
|
p_toc: .llong __toc_start + 0x8000 - 0b
|
|
|
|
/*
|
|
* This is where the main kernel code starts.
|
|
*/
|
|
_INIT_STATIC(start_here_multiplatform)
|
|
/* set up the TOC (real address) */
|
|
bl .relative_toc
|
|
|
|
/* Clear out the BSS. It may have been done in prom_init,
|
|
* already but that's irrelevant since prom_init will soon
|
|
* be detached from the kernel completely. Besides, we need
|
|
* to clear it now for kexec-style entry.
|
|
*/
|
|
LOAD_REG_ADDR(r11,__bss_stop)
|
|
LOAD_REG_ADDR(r8,__bss_start)
|
|
sub r11,r11,r8 /* bss size */
|
|
addi r11,r11,7 /* round up to an even double word */
|
|
srdi. r11,r11,3 /* shift right by 3 */
|
|
beq 4f
|
|
addi r8,r8,-8
|
|
li r0,0
|
|
mtctr r11 /* zero this many doublewords */
|
|
3: stdu r0,8(r8)
|
|
bdnz 3b
|
|
4:
|
|
|
|
#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
|
|
/* Setup OPAL entry */
|
|
std r28,0(r11);
|
|
std r29,8(r11);
|
|
#endif
|
|
|
|
#ifndef CONFIG_PPC_BOOK3E
|
|
mfmsr r6
|
|
ori r6,r6,MSR_RI
|
|
mtmsrd r6 /* RI on */
|
|
#endif
|
|
|
|
#ifdef CONFIG_RELOCATABLE
|
|
/* Save the physical address we're running at in kernstart_addr */
|
|
LOAD_REG_ADDR(r4, kernstart_addr)
|
|
clrldi r0,r25,2
|
|
std r0,0(r4)
|
|
#endif
|
|
|
|
/* The following gets the stack set up with the regs */
|
|
/* pointing to the real addr of the kernel stack. This is */
|
|
/* all done to support the C function call below which sets */
|
|
/* up the htab. This is done because we have relocated the */
|
|
/* kernel but are still running in real mode. */
|
|
|
|
LOAD_REG_ADDR(r3,init_thread_union)
|
|
|
|
/* set up a stack pointer */
|
|
addi r1,r3,THREAD_SIZE
|
|
li r0,0
|
|
stdu r0,-STACK_FRAME_OVERHEAD(r1)
|
|
|
|
/* Do very early kernel initializations, including initial hash table,
|
|
* stab and slb setup before we turn on relocation. */
|
|
|
|
/* Restore parameters passed from prom_init/kexec */
|
|
mr r3,r31
|
|
bl .early_setup /* also sets r13 and SPRG_PACA */
|
|
|
|
LOAD_REG_ADDR(r3, .start_here_common)
|
|
ld r4,PACAKMSR(r13)
|
|
mtspr SPRN_SRR0,r3
|
|
mtspr SPRN_SRR1,r4
|
|
RFI
|
|
b . /* prevent speculative execution */
|
|
|
|
/* This is where all platforms converge execution */
|
|
_INIT_GLOBAL(start_here_common)
|
|
/* relocation is on at this point */
|
|
std r1,PACAKSAVE(r13)
|
|
|
|
/* Load the TOC (virtual address) */
|
|
ld r2,PACATOC(r13)
|
|
|
|
bl .setup_system
|
|
|
|
/* Load up the kernel context */
|
|
5:
|
|
li r5,0
|
|
stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
|
|
#ifdef CONFIG_PPC_ISERIES
|
|
BEGIN_FW_FTR_SECTION
|
|
mfmsr r5
|
|
ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/
|
|
mtmsrd r5
|
|
li r5,1
|
|
END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
|
|
#endif
|
|
stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */
|
|
|
|
bl .start_kernel
|
|
|
|
/* Not reached */
|
|
BUG_OPCODE
|
|
|
|
/*
|
|
* We put a few things here that have to be page-aligned.
|
|
* This stuff goes at the beginning of the bss, which is page-aligned.
|
|
*/
|
|
.section ".bss"
|
|
|
|
.align PAGE_SHIFT
|
|
|
|
.globl empty_zero_page
|
|
empty_zero_page:
|
|
.space PAGE_SIZE
|
|
|
|
.globl swapper_pg_dir
|
|
swapper_pg_dir:
|
|
.space PGD_TABLE_SIZE
|