9ebc2935f3
It was the last platform under gt64120 and will fit better into the new platform makefile scheme, if moved. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
/*
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* pci.c: GT64120 PCI support.
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*
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* Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/gt64120.h>
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extern struct pci_ops gt64xxx_pci0_ops;
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static struct resource pci0_io_resource = {
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.name = "pci_0 io",
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.start = GT_PCI_IO_BASE,
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.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO,
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};
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static struct resource pci0_mem_resource = {
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.name = "pci_0 memory",
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.start = GT_PCI_MEM_BASE,
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.end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct pci_controller hose_0 = {
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.pci_ops = >64xxx_pci0_ops,
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.io_resource = &pci0_io_resource,
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.mem_resource = &pci0_mem_resource,
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};
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static int __init gt64120_pci_init(void)
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{
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u32 tmp;
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tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
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tmp = GT_READ(GT_PCI0_BARE_OFS);
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/* reset the whole PCI I/O space range */
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ioport_resource.start = GT_PCI_IO_BASE;
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ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
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register_pci_controller(&hose_0);
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return 0;
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}
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arch_initcall(gt64120_pci_init);
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