384cb2ce81
This patch adds clock driver of Exynos4415 SoC based on Cortex-A9 using common clock framework. The CMU (Clock Management Unit) of Exynos4415 controls PLLs(Phase Locked Loops) and generates system clocks for CPU, busses and function clocks for individual IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
360 lines
9.6 KiB
C
360 lines
9.6 KiB
C
/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Author: Chanwoo Choi <cw00.choi@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for Samsung Exynos4415 clock controllers.
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*/
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#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
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#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
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/*
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* Let each exported clock get a unique index, which is used on DT-enabled
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* platforms to lookup the clock from a clock specifier. These indices are
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* therefore considered an ABI and so must not be changed. This implies
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* that new clocks should be added either in free spaces between clock groups
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* or at the end.
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*/
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/*
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* Main CMU
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*/
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#define CLK_OSCSEL 1
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#define CLK_FIN_PLL 2
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#define CLK_FOUT_APLL 3
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#define CLK_FOUT_MPLL 4
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#define CLK_FOUT_EPLL 5
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#define CLK_FOUT_G3D_PLL 6
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#define CLK_FOUT_ISP_PLL 7
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#define CLK_FOUT_DISP_PLL 8
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/* Muxes */
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#define CLK_MOUT_MPLL_USER_L 16
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#define CLK_MOUT_GDL 17
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#define CLK_MOUT_MPLL_USER_R 18
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#define CLK_MOUT_GDR 19
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#define CLK_MOUT_EBI 20
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#define CLK_MOUT_ACLK_200 21
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#define CLK_MOUT_ACLK_160 22
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#define CLK_MOUT_ACLK_100 23
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#define CLK_MOUT_ACLK_266 24
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#define CLK_MOUT_G3D_PLL 25
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#define CLK_MOUT_EPLL 26
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#define CLK_MOUT_EBI_1 27
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#define CLK_MOUT_ISP_PLL 28
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#define CLK_MOUT_DISP_PLL 29
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#define CLK_MOUT_MPLL_USER_T 30
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#define CLK_MOUT_ACLK_400_MCUISP 31
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#define CLK_MOUT_G3D_PLLSRC 32
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#define CLK_MOUT_CSIS1 33
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#define CLK_MOUT_CSIS0 34
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#define CLK_MOUT_CAM1 35
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#define CLK_MOUT_FIMC3_LCLK 36
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#define CLK_MOUT_FIMC2_LCLK 37
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#define CLK_MOUT_FIMC1_LCLK 38
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#define CLK_MOUT_FIMC0_LCLK 39
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#define CLK_MOUT_MFC 40
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#define CLK_MOUT_MFC_1 41
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#define CLK_MOUT_MFC_0 42
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#define CLK_MOUT_G3D 43
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#define CLK_MOUT_G3D_1 44
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#define CLK_MOUT_G3D_0 45
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#define CLK_MOUT_MIPI0 46
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#define CLK_MOUT_FIMD0 47
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#define CLK_MOUT_TSADC_ISP 48
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#define CLK_MOUT_UART_ISP 49
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#define CLK_MOUT_SPI1_ISP 50
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#define CLK_MOUT_SPI0_ISP 51
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#define CLK_MOUT_PWM_ISP 52
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#define CLK_MOUT_AUDIO0 53
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#define CLK_MOUT_TSADC 54
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#define CLK_MOUT_MMC2 55
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#define CLK_MOUT_MMC1 56
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#define CLK_MOUT_MMC0 57
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#define CLK_MOUT_UART3 58
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#define CLK_MOUT_UART2 59
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#define CLK_MOUT_UART1 60
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#define CLK_MOUT_UART0 61
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#define CLK_MOUT_SPI2 62
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#define CLK_MOUT_SPI1 63
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#define CLK_MOUT_SPI0 64
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#define CLK_MOUT_SPDIF 65
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#define CLK_MOUT_AUDIO2 66
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#define CLK_MOUT_AUDIO1 67
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#define CLK_MOUT_MPLL_USER_C 68
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#define CLK_MOUT_HPM 69
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#define CLK_MOUT_CORE 70
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#define CLK_MOUT_APLL 71
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#define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72
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#define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73
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#define CLK_MOUT_JPEG 74
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#define CLK_MOUT_JPEG1 75
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#define CLK_MOUT_JPEG0 76
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#define CLK_MOUT_ACLK_ISP0_300 77
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#define CLK_MOUT_ACLK_ISP0_400 78
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#define CLK_MOUT_ACLK_ISP0_300_USER 79
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#define CLK_MOUT_ACLK_ISP1_300 80
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#define CLK_MOUT_ACLK_ISP1_300_USER 81
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#define CLK_MOUT_HDMI 82
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/* Dividers */
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#define CLK_DIV_GPL 90
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#define CLK_DIV_GDL 91
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#define CLK_DIV_GPR 92
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#define CLK_DIV_GDR 93
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#define CLK_DIV_ACLK_400_MCUISP 94
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#define CLK_DIV_EBI 95
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#define CLK_DIV_ACLK_200 96
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#define CLK_DIV_ACLK_160 97
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#define CLK_DIV_ACLK_100 98
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#define CLK_DIV_ACLK_266 99
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#define CLK_DIV_CSIS1 100
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#define CLK_DIV_CSIS0 101
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#define CLK_DIV_CAM1 102
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#define CLK_DIV_FIMC3_LCLK 103
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#define CLK_DIV_FIMC2_LCLK 104
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#define CLK_DIV_FIMC1_LCLK 105
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#define CLK_DIV_FIMC0_LCLK 106
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#define CLK_DIV_TV_BLK 107
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#define CLK_DIV_MFC 108
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#define CLK_DIV_G3D 109
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#define CLK_DIV_MIPI0_PRE 110
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#define CLK_DIV_MIPI0 111
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#define CLK_DIV_FIMD0 112
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#define CLK_DIV_UART_ISP 113
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#define CLK_DIV_SPI1_ISP_PRE 114
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#define CLK_DIV_SPI1_ISP 115
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#define CLK_DIV_SPI0_ISP_PRE 116
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#define CLK_DIV_SPI0_ISP 117
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#define CLK_DIV_PWM_ISP 118
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#define CLK_DIV_PCM0 119
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#define CLK_DIV_AUDIO0 120
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#define CLK_DIV_TSADC_PRE 121
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#define CLK_DIV_TSADC 122
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#define CLK_DIV_MMC1_PRE 123
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#define CLK_DIV_MMC1 124
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#define CLK_DIV_MMC0_PRE 125
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#define CLK_DIV_MMC0 126
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#define CLK_DIV_MMC2_PRE 127
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#define CLK_DIV_MMC2 128
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#define CLK_DIV_UART3 129
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#define CLK_DIV_UART2 130
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#define CLK_DIV_UART1 131
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#define CLK_DIV_UART0 132
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#define CLK_DIV_SPI1_PRE 133
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#define CLK_DIV_SPI1 134
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#define CLK_DIV_SPI0_PRE 135
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#define CLK_DIV_SPI0 136
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#define CLK_DIV_SPI2_PRE 137
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#define CLK_DIV_SPI2 138
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#define CLK_DIV_PCM2 139
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#define CLK_DIV_AUDIO2 140
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#define CLK_DIV_PCM1 141
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#define CLK_DIV_AUDIO1 142
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#define CLK_DIV_I2S1 143
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#define CLK_DIV_PXLASYNC_CSIS1_FIMC 144
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#define CLK_DIV_PXLASYNC_CSIS0_FIMC 145
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#define CLK_DIV_JPEG 146
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#define CLK_DIV_CORE2 147
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#define CLK_DIV_APLL 148
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#define CLK_DIV_PCLK_DBG 149
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#define CLK_DIV_ATB 150
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#define CLK_DIV_PERIPH 151
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#define CLK_DIV_COREM1 152
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#define CLK_DIV_COREM0 153
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#define CLK_DIV_CORE 154
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#define CLK_DIV_HPM 155
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#define CLK_DIV_COPY 156
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/* Gates */
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#define CLK_ASYNC_G3D 180
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#define CLK_ASYNC_MFCL 181
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#define CLK_ASYNC_TVX 182
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#define CLK_PPMULEFT 183
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#define CLK_GPIO_LEFT 184
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#define CLK_PPMUIMAGE 185
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#define CLK_QEMDMA2 186
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#define CLK_QEROTATOR 187
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#define CLK_SMMUMDMA2 188
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#define CLK_SMMUROTATOR 189
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#define CLK_MDMA2 190
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#define CLK_ROTATOR 191
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#define CLK_ASYNC_ISPMX 192
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#define CLK_ASYNC_MAUDIOX 193
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#define CLK_ASYNC_MFCR 194
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#define CLK_ASYNC_FSYSD 195
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#define CLK_ASYNC_LCD0X 196
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#define CLK_ASYNC_CAMX 197
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#define CLK_PPMURIGHT 198
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#define CLK_GPIO_RIGHT 199
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#define CLK_ANTIRBK_APBIF 200
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#define CLK_EFUSE_WRITER_APBIF 201
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#define CLK_MONOCNT 202
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#define CLK_TZPC6 203
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#define CLK_PROVISIONKEY1 204
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#define CLK_PROVISIONKEY0 205
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#define CLK_CMU_ISPPART 206
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#define CLK_TMU_APBIF 207
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#define CLK_KEYIF 208
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#define CLK_RTC 209
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#define CLK_WDT 210
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#define CLK_MCT 211
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#define CLK_SECKEY 212
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#define CLK_HDMI_CEC 213
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#define CLK_TZPC5 214
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#define CLK_TZPC4 215
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#define CLK_TZPC3 216
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#define CLK_TZPC2 217
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#define CLK_TZPC1 218
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#define CLK_TZPC0 219
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#define CLK_CMU_COREPART 220
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#define CLK_CMU_TOPPART 221
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#define CLK_PMU_APBIF 222
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#define CLK_SYSREG 223
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#define CLK_CHIP_ID 224
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#define CLK_SMMUFIMC_LITE2 225
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#define CLK_FIMC_LITE2 226
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#define CLK_PIXELASYNCM1 227
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#define CLK_PIXELASYNCM0 228
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#define CLK_PPMUCAMIF 229
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#define CLK_SMMUJPEG 230
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#define CLK_SMMUFIMC3 231
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#define CLK_SMMUFIMC2 232
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#define CLK_SMMUFIMC1 233
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#define CLK_SMMUFIMC0 234
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#define CLK_JPEG 235
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#define CLK_CSIS1 236
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#define CLK_CSIS0 237
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#define CLK_FIMC3 238
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#define CLK_FIMC2 239
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#define CLK_FIMC1 240
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#define CLK_FIMC0 241
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#define CLK_PPMUTV 242
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#define CLK_SMMUTV 243
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#define CLK_HDMI 244
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#define CLK_MIXER 245
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#define CLK_VP 246
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#define CLK_PPMUMFC_R 247
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#define CLK_PPMUMFC_L 248
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#define CLK_SMMUMFC_R 249
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#define CLK_SMMUMFC_L 250
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#define CLK_MFC 251
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#define CLK_PPMUG3D 252
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#define CLK_G3D 253
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#define CLK_PPMULCD0 254
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#define CLK_SMMUFIMD0 255
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#define CLK_DSIM0 256
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#define CLK_SMIES 257
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#define CLK_MIE0 258
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#define CLK_FIMD0 259
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#define CLK_TSADC 260
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#define CLK_PPMUFILE 261
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#define CLK_NFCON 262
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#define CLK_USBDEVICE 263
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#define CLK_USBHOST 264
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#define CLK_SROMC 265
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#define CLK_SDMMC2 266
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#define CLK_SDMMC1 267
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#define CLK_SDMMC0 268
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#define CLK_PDMA1 269
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#define CLK_PDMA0 270
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#define CLK_SPDIF 271
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#define CLK_PWM 272
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#define CLK_PCM2 273
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#define CLK_PCM1 274
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#define CLK_I2S1 275
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#define CLK_SPI2 276
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#define CLK_SPI1 277
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#define CLK_SPI0 278
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#define CLK_I2CHDMI 279
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#define CLK_I2C7 280
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#define CLK_I2C6 281
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#define CLK_I2C5 282
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#define CLK_I2C4 283
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#define CLK_I2C3 284
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#define CLK_I2C2 285
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#define CLK_I2C1 286
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#define CLK_I2C0 287
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#define CLK_UART3 288
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#define CLK_UART2 289
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#define CLK_UART1 290
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#define CLK_UART0 291
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/* Special clocks */
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#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330
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#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331
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#define CLK_SCLK_JPEG 332
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#define CLK_SCLK_CSIS1 333
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#define CLK_SCLK_CSIS0 334
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#define CLK_SCLK_CAM1 335
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#define CLK_SCLK_FIMC3_LCLK 336
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#define CLK_SCLK_FIMC2_LCLK 337
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#define CLK_SCLK_FIMC1_LCLK 338
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#define CLK_SCLK_FIMC0_LCLK 339
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#define CLK_SCLK_PIXEL 340
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#define CLK_SCLK_HDMI 341
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#define CLK_SCLK_MIXER 342
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#define CLK_SCLK_MFC 343
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#define CLK_SCLK_G3D 344
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#define CLK_SCLK_MIPIDPHY4L 345
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#define CLK_SCLK_MIPI0 346
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#define CLK_SCLK_MDNIE0 347
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#define CLK_SCLK_FIMD0 348
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#define CLK_SCLK_PCM0 349
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#define CLK_SCLK_AUDIO0 350
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#define CLK_SCLK_TSADC 351
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#define CLK_SCLK_EBI 352
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#define CLK_SCLK_MMC2 353
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#define CLK_SCLK_MMC1 354
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#define CLK_SCLK_MMC0 355
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#define CLK_SCLK_I2S 356
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#define CLK_SCLK_PCM2 357
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#define CLK_SCLK_PCM1 358
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#define CLK_SCLK_AUDIO2 359
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#define CLK_SCLK_AUDIO1 360
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#define CLK_SCLK_SPDIF 361
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#define CLK_SCLK_SPI2 362
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#define CLK_SCLK_SPI1 363
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#define CLK_SCLK_SPI0 364
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#define CLK_SCLK_UART3 365
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#define CLK_SCLK_UART2 366
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#define CLK_SCLK_UART1 367
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#define CLK_SCLK_UART0 368
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#define CLK_SCLK_HDMIPHY 369
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/*
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* Total number of clocks of main CMU.
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* NOTE: Must be equal to last clock ID increased by one.
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*/
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#define CLK_NR_CLKS 370
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/*
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* CMU DMC
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*/
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#define CLK_DMC_FOUT_MPLL 1
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#define CLK_DMC_FOUT_BPLL 2
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#define CLK_DMC_MOUT_MPLL 3
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#define CLK_DMC_MOUT_BPLL 4
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#define CLK_DMC_MOUT_DPHY 5
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#define CLK_DMC_MOUT_DMC_BUS 6
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#define CLK_DMC_DIV_DMC 7
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#define CLK_DMC_DIV_DPHY 8
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#define CLK_DMC_DIV_DMC_PRE 9
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#define CLK_DMC_DIV_DMCP 10
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#define CLK_DMC_DIV_DMCD 11
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#define CLK_DMC_DIV_MPLL_PRE 12
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/*
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* Total number of clocks of CMU_DMC.
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* NOTE: Must be equal to highest clock ID increased by one.
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*/
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#define NR_CLKS_DMC 13
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#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */
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