c7d3555ac0
Loongson family machines use Hyper-Transport bus for inter-core connection and device connection. The PCI bus is a subordinate linked at HT1. With LEFI firmware interface, We don't need fixup for PCI irq routing (except providing a VBIOS of the integrated GPU). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6633 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
55 lines
1.7 KiB
C
55 lines
1.7 KiB
C
/*
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* Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
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* Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
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*
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* This program is free software; you can redistribute it
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* and/or modify it under the terms of the GNU General
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* Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __ASM_MACH_LOONGSON_PCI_H_
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#define __ASM_MACH_LOONGSON_PCI_H_
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extern struct pci_ops loongson_pci_ops;
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/* this is an offset from mips_io_port_base */
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#define LOONGSON_PCI_IO_START 0x00004000UL
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#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
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/*
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* we use address window2 to map cpu address space to pci space
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* window2: cpu [1G, 2G] -> pci [1G, 2G]
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* why not use window 0 & 1? because they are used by cpu when booting.
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* window0: cpu [0, 256M] -> ddr [0, 256M]
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* window1: cpu [256M, 512M] -> pci [256M, 512M]
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*/
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/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
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#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
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#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
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#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
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#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
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#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
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LOONGSON_PCI_MEM_START + 1)
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#else /* loongson2f/32bit & loongson2e */
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/* this pci memory space is mapped by pcimap in pci.c */
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#ifdef CONFIG_CPU_LOONGSON3
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#define LOONGSON_PCI_MEM_START 0x40000000UL
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#define LOONGSON_PCI_MEM_END 0x7effffffUL
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#else
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#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
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#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
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#endif
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/* this is an offset from mips_io_port_base */
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#define LOONGSON_PCI_IO_START 0x00004000UL
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#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
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#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */
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