b3623080ff
This corrects a logic-error that I made in the original implementation. An alternate patch would be to just remove these lines and leave the clock running as it is reconfigured later on during boot anyway. Signed-off-by: Simon Horman <horms@verge.net.au> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
95 lines
2.7 KiB
C
95 lines
2.7 KiB
C
/*
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* SuperH Mobile SDHI
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2010 Kuninori Morimoto
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* Copyright (C) 2010 Simon Horman
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Parts inspired by u-boot
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*/
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#include <linux/io.h>
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#include <mach/mmc.h>
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#include <linux/mmc/boot.h>
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#include <linux/mmc/tmio.h>
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#include "sdhi-shmobile.h"
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#define PORT179CR 0xe60520b3
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#define PORT180CR 0xe60520b4
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#define PORT181CR 0xe60520b5
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#define PORT182CR 0xe60520b6
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#define PORT183CR 0xe60520b7
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#define PORT184CR 0xe60520b8
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#define SMSTPCR3 0xe615013c
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#define CR_INPUT_ENABLE 0x10
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#define CR_FUNCTION1 0x01
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#define SDHI1_BASE (void __iomem *)0xe6860000
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#define SDHI_BASE SDHI1_BASE
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/* SuperH Mobile SDHI loader
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*
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* loads the zImage from an SD card starting from block 0
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* on physical partition 1
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*
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* The image must be start with a vrl4 header and
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* the zImage must start at offset 512 of the image. That is,
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* at block 1 (=byte 512) of physical partition 1
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*
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* Use the following line to write the vrl4 formated zImage
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* to an SD card
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* # dd if=vrl4.out of=/dev/sdx bs=512
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*/
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asmlinkage void mmc_loader(unsigned short *buf, unsigned long len)
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{
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int high_capacity;
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mmc_init_progress();
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mmc_update_progress(MMC_PROGRESS_ENTER);
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/* Initialise SDHI1 */
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/* PORT184CR: GPIO_FN_SDHICMD1 Control */
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__raw_writeb(CR_FUNCTION1, PORT184CR);
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/* PORT179CR: GPIO_FN_SDHICLK1 Control */
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__raw_writeb(CR_INPUT_ENABLE|CR_FUNCTION1, PORT179CR);
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/* PORT181CR: GPIO_FN_SDHID1_3 Control */
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__raw_writeb(CR_FUNCTION1, PORT183CR);
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/* PORT182CR: GPIO_FN_SDHID1_2 Control */
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__raw_writeb(CR_FUNCTION1, PORT182CR);
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/* PORT183CR: GPIO_FN_SDHID1_1 Control */
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__raw_writeb(CR_FUNCTION1, PORT181CR);
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/* PORT180CR: GPIO_FN_SDHID1_0 Control */
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__raw_writeb(CR_FUNCTION1, PORT180CR);
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/* Enable clock to SDHI1 hardware block */
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__raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 13), SMSTPCR3);
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/* setup SDHI hardware */
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mmc_update_progress(MMC_PROGRESS_INIT);
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high_capacity = sdhi_boot_init(SDHI_BASE);
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if (high_capacity < 0)
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goto err;
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mmc_update_progress(MMC_PROGRESS_LOAD);
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/* load kernel */
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if (sdhi_boot_do_read(SDHI_BASE, high_capacity,
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0, /* Kernel is at block 1 */
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(len + TMIO_BBS - 1) / TMIO_BBS, buf))
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goto err;
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/* Disable clock to SDHI1 hardware block */
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__raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3);
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mmc_update_progress(MMC_PROGRESS_DONE);
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return;
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err:
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for(;;);
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}
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