238 lines
		
	
	
	
		
			6.9 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			238 lines
		
	
	
	
		
			6.9 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *
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|  * BRIEF MODULE DESCRIPTION
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|  *      A DMA channel allocator for Au1x00. API is modeled loosely off of
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|  *      linux/kernel/dma.c.
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|  *
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|  * Copyright 2000, 2008 MontaVista Software Inc.
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|  * Author: MontaVista Software, Inc. <source@mvista.com>
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|  * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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|  *
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|  *  This program is free software; you can redistribute  it and/or modify it
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|  *  under  the terms of  the GNU General  Public License as published by the
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|  *  Free Software Foundation;  either version 2 of the  License, or (at your
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|  *  option) any later version.
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|  *
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|  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
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|  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
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|  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
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|  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
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|  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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|  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
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|  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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|  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
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|  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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|  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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|  *
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|  *  You should have received a copy of the  GNU General Public License along
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|  *  with this program; if not, write  to the Free Software Foundation, Inc.,
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|  *  675 Mass Ave, Cambridge, MA 02139, USA.
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|  *
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|  */
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| #include <linux/module.h>
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| #include <linux/kernel.h>
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| #include <linux/errno.h>
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| #include <linux/spinlock.h>
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| #include <linux/interrupt.h>
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| 
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| #include <asm/mach-au1x00/au1000.h>
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| #include <asm/mach-au1x00/au1000_dma.h>
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| 
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| #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
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|     defined(CONFIG_SOC_AU1100)
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| /*
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|  * A note on resource allocation:
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|  *
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|  * All drivers needing DMA channels, should allocate and release them
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|  * through the public routines `request_dma()' and `free_dma()'.
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|  *
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|  * In order to avoid problems, all processes should allocate resources in
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|  * the same sequence and release them in the reverse order.
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|  *
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|  * So, when allocating DMAs and IRQs, first allocate the DMA, then the IRQ.
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|  * When releasing them, first release the IRQ, then release the DMA. The
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|  * main reason for this order is that, if you are requesting the DMA buffer
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|  * done interrupt, you won't know the irq number until the DMA channel is
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|  * returned from request_dma.
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|  */
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| 
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| DEFINE_SPINLOCK(au1000_dma_spin_lock);
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| 
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| struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
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|       {.dev_id = -1,},
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|       {.dev_id = -1,},
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|       {.dev_id = -1,},
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|       {.dev_id = -1,},
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|       {.dev_id = -1,},
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|       {.dev_id = -1,},
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|       {.dev_id = -1,},
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|       {.dev_id = -1,}
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| };
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| EXPORT_SYMBOL(au1000_dma_table);
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| 
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| /* Device FIFO addresses and default DMA modes */
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| static const struct dma_dev {
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| 	unsigned int fifo_addr;
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| 	unsigned int dma_mode;
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| } dma_dev_table[DMA_NUM_DEV] = {
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| 	{UART0_ADDR + UART_TX, 0},
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| 	{UART0_ADDR + UART_RX, 0},
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| 	{0, 0},
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| 	{0, 0},
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| 	{AC97C_DATA, DMA_DW16 },          /* coherent */
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| 	{AC97C_DATA, DMA_DR | DMA_DW16 }, /* coherent */
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| 	{UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC},
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| 	{UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC},
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| 	{USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC},
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| 	{USBD_EP0WR, DMA_DW8 | DMA_NC},
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| 	{USBD_EP2WR, DMA_DW8 | DMA_NC},
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| 	{USBD_EP3WR, DMA_DW8 | DMA_NC},
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| 	{USBD_EP4RD, DMA_DR | DMA_DW8 | DMA_NC},
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| 	{USBD_EP5RD, DMA_DR | DMA_DW8 | DMA_NC},
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| 	{I2S_DATA, DMA_DW32 | DMA_NC},
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| 	{I2S_DATA, DMA_DR | DMA_DW32 | DMA_NC}
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| };
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| 
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| int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
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| 			 int length, int *eof, void *data)
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| {
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| 	int i, len = 0;
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| 	struct dma_chan *chan;
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| 
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| 	for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
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| 		chan = get_dma_chan(i);
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| 		if (chan != NULL)
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| 			len += sprintf(buf + len, "%2d: %s\n",
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| 				       i, chan->dev_str);
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| 	}
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| 
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| 	if (fpos >= len) {
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| 		*start = buf;
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| 		*eof = 1;
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| 		return 0;
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| 	}
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| 	*start = buf + fpos;
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| 	len -= fpos;
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| 	if (len > length)
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| 		return length;
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| 	*eof = 1;
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| 	return len;
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| }
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| 
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| /* Device FIFO addresses and default DMA modes - 2nd bank */
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| static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = {
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| 	{ SD0_XMIT_FIFO, DMA_DS | DMA_DW8 },		/* coherent */
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| 	{ SD0_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 },	/* coherent */
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| 	{ SD1_XMIT_FIFO, DMA_DS | DMA_DW8 },		/* coherent */
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| 	{ SD1_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 }	/* coherent */
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| };
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| 
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| void dump_au1000_dma_channel(unsigned int dmanr)
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| {
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| 	struct dma_chan *chan;
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| 
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| 	if (dmanr >= NUM_AU1000_DMA_CHANNELS)
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| 		return;
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| 	chan = &au1000_dma_table[dmanr];
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| 
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| 	printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
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| 	printk(KERN_INFO "  mode = 0x%08x\n",
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| 	       au_readl(chan->io + DMA_MODE_SET));
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| 	printk(KERN_INFO "  addr = 0x%08x\n",
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| 	       au_readl(chan->io + DMA_PERIPHERAL_ADDR));
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| 	printk(KERN_INFO "  start0 = 0x%08x\n",
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| 	       au_readl(chan->io + DMA_BUFFER0_START));
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| 	printk(KERN_INFO "  start1 = 0x%08x\n",
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| 	       au_readl(chan->io + DMA_BUFFER1_START));
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| 	printk(KERN_INFO "  count0 = 0x%08x\n",
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| 	       au_readl(chan->io + DMA_BUFFER0_COUNT));
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| 	printk(KERN_INFO "  count1 = 0x%08x\n",
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| 	       au_readl(chan->io + DMA_BUFFER1_COUNT));
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| }
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| 
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| /*
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|  * Finds a free channel, and binds the requested device to it.
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|  * Returns the allocated channel number, or negative on error.
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|  * Requests the DMA done IRQ if irqhandler != NULL.
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|  */
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| int request_au1000_dma(int dev_id, const char *dev_str,
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| 		       irq_handler_t irqhandler,
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| 		       unsigned long irqflags,
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| 		       void *irq_dev_id)
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| {
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| 	struct dma_chan *chan;
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| 	const struct dma_dev *dev;
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| 	int i, ret;
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| 
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| #if defined(CONFIG_SOC_AU1100)
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| 	if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
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| 		return -EINVAL;
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| #else
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| 	if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
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| 		return -EINVAL;
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| #endif
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| 
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| 	for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
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| 		if (au1000_dma_table[i].dev_id < 0)
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| 			break;
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| 
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| 	if (i == NUM_AU1000_DMA_CHANNELS)
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| 		return -ENODEV;
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| 
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| 	chan = &au1000_dma_table[i];
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| 
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| 	if (dev_id >= DMA_NUM_DEV) {
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| 		dev_id -= DMA_NUM_DEV;
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| 		dev = &dma_dev_table_bank2[dev_id];
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| 	} else
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| 		dev = &dma_dev_table[dev_id];
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| 
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| 	if (irqhandler) {
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| 		chan->irq = AU1000_DMA_INT_BASE + i;
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| 		chan->irq_dev = irq_dev_id;
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| 		ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,
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| 				  chan->irq_dev);
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| 		if (ret) {
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| 			chan->irq = 0;
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| 			chan->irq_dev = NULL;
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| 			return ret;
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| 		}
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| 	} else {
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| 		chan->irq = 0;
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| 		chan->irq_dev = NULL;
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| 	}
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| 
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| 	/* fill it in */
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| 	chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN;
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| 	chan->dev_id = dev_id;
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| 	chan->dev_str = dev_str;
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| 	chan->fifo_addr = dev->fifo_addr;
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| 	chan->mode = dev->dma_mode;
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| 
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| 	/* initialize the channel before returning */
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| 	init_dma(i);
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| 
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| 	return i;
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| }
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| EXPORT_SYMBOL(request_au1000_dma);
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| 
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| void free_au1000_dma(unsigned int dmanr)
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| {
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| 	struct dma_chan *chan = get_dma_chan(dmanr);
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| 
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| 	if (!chan) {
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| 		printk(KERN_ERR "Error trying to free DMA%d\n", dmanr);
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| 		return;
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| 	}
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| 
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| 	disable_dma(dmanr);
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| 	if (chan->irq)
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| 		free_irq(chan->irq, chan->irq_dev);
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| 
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| 	chan->irq = 0;
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| 	chan->irq_dev = NULL;
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| 	chan->dev_id = -1;
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| }
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| EXPORT_SYMBOL(free_au1000_dma);
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| 
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| #endif /* AU1000 AU1500 AU1100 */
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