From 975a6b9423ca0bc076ae3a771ac2caa1727b5522 Mon Sep 17 00:00:00 2001 From: Maximilian Weigand Date: Mon, 25 Nov 2024 19:19:09 +0800 Subject: [PATCH 01/10] Pinenote DTS: Add a few fixes that help with Bluetooth audio * define dma-names for uart1 (tx, rx) * fix bluetooth dts entry (as suggested by user hrdl and from the q64a dts) Signed-off-by: Maximilian Weigand --- arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 9 ++++++--- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 1 + 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index 690253640098..d7cd81dce6eb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -988,16 +988,19 @@ pinctrl-names = "default"; uart-has-rtscts; status = "okay"; + rx-threshold = <1>; + tx-threshold = <1>; bluetooth { compatible = "brcm,bcm43438-bt"; clocks = <&rk817 1>; clock-names = "lpo"; - device-wakeup-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; pinctrl-0 = <&bt_enable_h>, <&bt_host_wake_l>, <&bt_wake_h>; pinctrl-names = "default"; - shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; vbat-supply = <&vcc_wl>; vddio-supply = <&vcca_1v8_pmu>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index b8427813b68c..e795fc50279d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1430,6 +1430,7 @@ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; pinctrl-0 = <&uart1m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; From 6530370a3ca1f8ec95829fa1b1ed42794d43341d Mon Sep 17 00:00:00 2001 From: Maximilian Weigand Date: Sun, 11 Feb 2024 22:46:25 +0100 Subject: [PATCH 02/10] pinenote: request a few clock frequencies to run hclk_ebc at 300 MHz --- arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index d7cd81dce6eb..e73b76bf3e15 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -308,6 +308,17 @@ }; }; +&cru { + // assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru ACLK_RGA_PRE>, <&cru HCLK_RGA_PRE>; + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru ACLK_RGA_PRE>, <&cru CPLL_250M>, <&cru HCLK_RGA_PRE>, <&cru HCLK_EBC>, <&cru HCLK_JENC>; + // assigned-clock-rates = <32768>, <1200000000>, <200000000>, <300000000>, <300000000>; + // assigned-clock-rates = <32768>, <1200000000>, <200000000>, <250000000>, <250000000>, <250000000>, <250000000>, <250000000>; + assigned-clock-rates = <32768>, <1200000000>, <200000000>, <300000000>, <300000000>, <300000000>, <300000000>, <300000000>; + // stronger artifacting, I suspend instabilities due to too high clock frequencies + // assigned-clock-rates = <32768>, <1200000000>, <200000000>, <333400000>, <333400000>, <333400000>, <333400000>, <333400000>; + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; +}; + &cpu0 { cpu-supply = <&vdd_cpu>; }; From 7f93a48b73ea989a5109b2baceb7512d6adcde52 Mon Sep 17 00:00:00 2001 From: Maximilian Weigand Date: Fri, 23 Feb 2024 19:52:54 +0100 Subject: [PATCH 03/10] Pinenote: modify frequencies of ACLK_TOP_HIGH and CLK_TOP_LOW to match android Previously, we defaulted to 200 MHz (TOP_LOW) and 300 MHz (TOP_HIGH). However, the rockchip android kernel uses 500 and 400 MHz, respectively. --- arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index e73b76bf3e15..49ba69b8a431 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -310,10 +310,20 @@ &cru { // assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru ACLK_RGA_PRE>, <&cru HCLK_RGA_PRE>; - assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru ACLK_RGA_PRE>, <&cru CPLL_250M>, <&cru HCLK_RGA_PRE>, <&cru HCLK_EBC>, <&cru HCLK_JENC>; + assigned-clocks = <&pmucru CLK_RTC_32K>, + <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, + <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, + <&cru ACLK_RGA_PRE>, <&cru CPLL_250M>, + <&cru HCLK_RGA_PRE>, <&cru HCLK_EBC>, + <&cru HCLK_JENC>; // assigned-clock-rates = <32768>, <1200000000>, <200000000>, <300000000>, <300000000>; // assigned-clock-rates = <32768>, <1200000000>, <200000000>, <250000000>, <250000000>, <250000000>, <250000000>, <250000000>; - assigned-clock-rates = <32768>, <1200000000>, <200000000>, <300000000>, <300000000>, <300000000>, <300000000>, <300000000>; + assigned-clock-rates = <32768>, + <500000000>, <400000000>, + <1200000000>, <200000000>, + <300000000>, <300000000>, + <300000000>, <300000000>, + <300000000>; // stronger artifacting, I suspend instabilities due to too high clock frequencies // assigned-clock-rates = <32768>, <1200000000>, <200000000>, <333400000>, <333400000>, <333400000>, <333400000>, <333400000>; assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; From af9d91094e94ad8e76b01640b2383f8a341d2750 Mon Sep 17 00:00:00 2001 From: Maximilian Weigand Date: Fri, 5 Jul 2024 19:34:26 +0800 Subject: [PATCH 04/10] dts: rk356x: remove unused/duplicate rk_rga node The node actually used is just called rga --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index e795fc50279d..b7db7fc02f8f 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -630,23 +630,6 @@ power-domains = <&power RK3568_PD_VPU>; }; - rk_rga: rk_rga@fdeb0000 { - compatible = "rockchip,rk356x-rga"; - reg = <0x0 0xfdeb0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; - clock-names = "aclk_rga", "hclk_rga", "clk_rga"; - power-domains = <&power RK3568_PD_RGA>; - /* 754 #define SRST_A_RGA 292 */ - /* 755 #define SRST_H_RGA 293 */ - /* 756 #define SRST_RGA_CORE 294 */ - /* resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; */ - /* reset-names = "core", "axi", "ahb"; */ - // from the documenation: - // dma-coherent; - status = "disabled"; - }; - ebc: ebc@fdec0000 { compatible = "rockchip,rk3568-ebc"; reg = <0x0 0xfdec0000 0x0 0x5000>; From 011b9f3070ca20ff0fc539f9f1148284beaeb251 Mon Sep 17 00:00:00 2001 From: Maximilian Weigand Date: Fri, 5 Jul 2024 19:36:53 +0800 Subject: [PATCH 05/10] dts: pinenote: always leave vdd_gpu_npu: DCDC_REG2 on We had problems with the gpu being permanently disabled if not used within 30 seconds after boot.... --- arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index 49ba69b8a431..fc81a965d5f4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -450,6 +450,7 @@ vdd_gpu_npu: DCDC_REG2 { regulator-name = "vdd_gpu_npu"; + regulator-always-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; regulator-ramp-delay = <6001>; From c16c75f42dc21a8995831d7b4e0cd170c569def3 Mon Sep 17 00:00:00 2001 From: Maximilian Weigand Date: Fri, 5 Jul 2024 19:56:39 +0800 Subject: [PATCH 06/10] rk3566-pinenote.dtsi: remove rk_rga node overlay --- arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index fc81a965d5f4..2f915803620e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -368,10 +368,6 @@ status = "okay"; }; -&rk_rga{ - status = "disabled"; -}; - &i2c0 { status = "okay"; From 651c85f055caaf22c25013401badf8d128c3aec1 Mon Sep 17 00:00:00 2001 From: Maximilian Weigand Date: Fri, 5 Jul 2024 20:40:45 +0800 Subject: [PATCH 07/10] dts: pinenote: activate rga hardware by default --- arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index 2f915803620e..f9310d9588a1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -1046,3 +1046,7 @@ }; }; }; + +&rga { + status = "okay"; +}; From 35dc1e560523115e2069025c99889b8b66f2635c Mon Sep 17 00:00:00 2001 From: hrdl <31923882+hrdl-github@users.noreply.github.com> Date: Thu, 9 Jan 2025 01:55:29 +0100 Subject: [PATCH 08/10] rk3566-pinenote.dtsi: set CPLL_333M to 33.33 MHZ and use in rockchip_ebc direct mode This allows the panel to be run at the recommended 33.33 MHz sclk, decreasing frame processing times by a bit more than a ms. This only works in direct mode by setting EBC_DSP_CTRL_DSP_SDCLK_DIV to 0. This behaviour is not documented in the Rockchip RK3568 TRM, but is used by the Lenovo Smart Paper. LUT mode and 3WIN mode are not compatible with this setting and need to be run at sclk 25 MHz (dclk 200 MHz, clock divider of 8). Previously 31.25 MHz were supported by setting dclk to 250 MHz, which resulted in CPLL_333M to be set to 250 MHz. --- arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index f9310d9588a1..f26ac9c0f2cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -315,7 +315,7 @@ <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru ACLK_RGA_PRE>, <&cru CPLL_250M>, <&cru HCLK_RGA_PRE>, <&cru HCLK_EBC>, - <&cru HCLK_JENC>; + <&cru HCLK_JENC>, <&cru CPLL_333M>; // assigned-clock-rates = <32768>, <1200000000>, <200000000>, <300000000>, <300000000>; // assigned-clock-rates = <32768>, <1200000000>, <200000000>, <250000000>, <250000000>, <250000000>, <250000000>, <250000000>; assigned-clock-rates = <32768>, @@ -323,7 +323,7 @@ <1200000000>, <200000000>, <300000000>, <300000000>, <300000000>, <300000000>, - <300000000>; + <300000000>, <33333334>; // stronger artifacting, I suspend instabilities due to too high clock frequencies // assigned-clock-rates = <32768>, <1200000000>, <200000000>, <333400000>, <333400000>, <333400000>, <333400000>, <333400000>; assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; From c9b5622e0d24728e3e52489c3aad5e5831f6807d Mon Sep 17 00:00:00 2001 From: hrdl <31923882+hrdl-github@users.noreply.github.com> Date: Thu, 9 Jan 2025 02:33:24 +0100 Subject: [PATCH 09/10] rockchip_ebc: adjust cpll_333m and enhance clock management diff mode works best with dclk 33.33 MHz using cpll_333m 33.33 MHz. The remaining modes work best at 8 * 33.33 MHz = 266.67 Mhz. By default 200 MHz can be obtained by using gpll_200m as parent at 200 MHz. Alternatively cpll_333m can be used at 250 MHz, resulting in a noticable speedup. --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index b7db7fc02f8f..c02b24735887 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -634,8 +634,8 @@ compatible = "rockchip,rk3568-ebc"; reg = <0x0 0xfdec0000 0x0 0x5000>; interrupts = ; - clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>; - clock-names = "hclk", "dclk"; + clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>, <&cru CPLL_333M>; + clock-names = "hclk", "dclk", "cpll_333m"; pinctrl-0 = <&ebc_pins>; pinctrl-names = "default"; power-domains = <&power RK3568_PD_RGA>; From 6f680296674101ffb7db7bd81c8cbd9f6a73fff1 Mon Sep 17 00:00:00 2001 From: hrdl <31923882+hrdl-github@users.noreply.github.com> Date: Mon, 13 Jan 2025 18:02:26 +0100 Subject: [PATCH 10/10] rk3566-pinenote.dtsi: adjust CPLL_250M Set CPLL_250M to 250 MHz as intended. --- arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index f26ac9c0f2cf..95193aa359b8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -321,7 +321,7 @@ assigned-clock-rates = <32768>, <500000000>, <400000000>, <1200000000>, <200000000>, - <300000000>, <300000000>, + <300000000>, <250000000>, <300000000>, <300000000>, <300000000>, <33333334>; // stronger artifacting, I suspend instabilities due to too high clock frequencies