diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
index 690253640098..95193aa359b8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
@@ -308,6 +308,27 @@
 	};
 };
 
+&cru {
+		// assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru ACLK_RGA_PRE>, <&cru HCLK_RGA_PRE>;
+		assigned-clocks = <&pmucru CLK_RTC_32K>,
+  			<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
+			<&cru PLL_GPLL>, <&pmucru PLL_PPLL>,
+ 			<&cru ACLK_RGA_PRE>, <&cru CPLL_250M>,
+			<&cru HCLK_RGA_PRE>, <&cru HCLK_EBC>,
+		    <&cru HCLK_JENC>, <&cru CPLL_333M>;
+		// assigned-clock-rates = <32768>, <1200000000>, <200000000>, <300000000>, <300000000>;
+		// assigned-clock-rates = <32768>, <1200000000>, <200000000>, <250000000>, <250000000>, <250000000>, <250000000>, <250000000>;
+		assigned-clock-rates = <32768>,
+				<500000000>, <400000000>,
+				 <1200000000>, <200000000>,
+				 <300000000>, <250000000>,
+				 <300000000>, <300000000>,
+				 <300000000>, <33333334>;
+		// stronger artifacting, I suspend instabilities due to too high clock frequencies
+		// assigned-clock-rates = <32768>, <1200000000>, <200000000>, <333400000>, <333400000>, <333400000>, <333400000>, <333400000>;
+		assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
+};
+
 &cpu0 {
 	cpu-supply = <&vdd_cpu>;
 };
@@ -347,10 +368,6 @@
 	status = "okay";
 };
 
-&rk_rga{
-       status = "disabled";
-};
-
 &i2c0 {
 	status = "okay";
 
@@ -429,6 +446,7 @@
 
 			vdd_gpu_npu: DCDC_REG2 {
 				regulator-name = "vdd_gpu_npu";
+				regulator-always-on;
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <1350000>;
 				regulator-ramp-delay = <6001>;
@@ -988,16 +1006,19 @@
 	pinctrl-names = "default";
 	uart-has-rtscts;
 	status = "okay";
+	rx-threshold = <1>;
+	tx-threshold = <1>;
 
 	bluetooth {
 		compatible = "brcm,bcm43438-bt";
 		clocks = <&rk817 1>;
 		clock-names = "lpo";
-		device-wakeup-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
-		host-wakeup-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+        host-wakeup-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+        device-wakeup-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+        shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+        max-speed = <3000000>;
 		pinctrl-0 = <&bt_enable_h>, <&bt_host_wake_l>, <&bt_wake_h>;
 		pinctrl-names = "default";
-		shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
 		vbat-supply = <&vcc_wl>;
 		vddio-supply = <&vcca_1v8_pmu>;
 	};
@@ -1025,3 +1046,7 @@
 		};
 	};
 };
+
+&rga {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
index b8427813b68c..c02b24735887 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
@@ -630,29 +630,12 @@
 		power-domains = <&power RK3568_PD_VPU>;
 	};
 
-	rk_rga: rk_rga@fdeb0000 {
-		compatible = "rockchip,rk356x-rga";
-		reg = <0x0 0xfdeb0000 0x0 0x1000>;
-		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
-		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
-		power-domains = <&power RK3568_PD_RGA>;
-		/* 754 #define SRST_A_RGA      292 */
-		/* 755 #define SRST_H_RGA      293 */
-		/* 756 #define SRST_RGA_CORE       294 */
-		/* resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; */
-		/* reset-names = "core", "axi", "ahb"; */
-		// from the documenation:
-		// dma-coherent;
-		status = "disabled";
-	};
-
 	ebc: ebc@fdec0000 {
 		compatible = "rockchip,rk3568-ebc";
 		reg = <0x0 0xfdec0000 0x0 0x5000>;
 		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>;
-		clock-names = "hclk", "dclk";
+		clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>, <&cru CPLL_333M>;
+		clock-names = "hclk", "dclk", "cpll_333m";
 		pinctrl-0 = <&ebc_pins>;
 		pinctrl-names = "default";
 		power-domains = <&power RK3568_PD_RGA>;
@@ -1430,6 +1413,7 @@
 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac0 2>, <&dmac0 3>;
+		dma-names = "tx", "rx";
 		pinctrl-0 = <&uart1m0_xfer>;
 		pinctrl-names = "default";
 		reg-io-width = <4>;